arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+)
   2 /*
   3  * Copyright (C) 2015-2019 DH electronics GmbH
   4  * Copyright (C) 2018 Marek Vasut <marex@denx.de>
   5  */
   6
   7 #include "imx6qdl-dhcom.dtsi"
   8
   9 / {
  10         chosen {
  11                 stdout-path = &uart1;
  12         };
  13
  14         clk_ext_audio_codec: clock-codec {
  15                 compatible = "fixed-clock";
  16                 #clock-cells = <0>;
  17                 clock-frequency = <24000000>;
  18         };
  19
  20         sound {
  21                 compatible = "fsl,imx-audio-sgtl5000";
  22                 model = "imx-sgtl5000";
  23                 ssi-controller = <&ssi1>;
  24                 audio-codec = <&sgtl5000>;
  25                 audio-routing =
  26                         "MIC_IN", "Mic Jack",
  27                         "Mic Jack", "Mic Bias",
  28                         "LINE_IN", "Line In Jack",
  29                         "Headphone Jack", "HP_OUT";
  30                 mux-int-port = <1>;
  31                 mux-ext-port = <3>;
  32         };
  33 };
  34
  35 &audmux {
  36         pinctrl-names = "default";
  37         pinctrl-0 = <&pinctrl_audmux_ext>;
  38         status = "okay";
  39 };
  40
  41 &hdmi {
  42         ddc-i2c-bus = <&i2c2>;
  43         status = "okay";
  44 };
  45
  46 &i2c2 {
  47         sgtl5000: codec@a {
  48                 compatible = "fsl,sgtl5000";
  49                 reg = <0x0a>;
  50                 #sound-dai-cells = <0>;
  51                 clocks = <&clk_ext_audio_codec>;
  52                 VDDA-supply = <&reg_3p3v>;
  53                 VDDIO-supply = <&reg_3p3v>;
  54         };
  55 };
  56
  57 &iomuxc {
  58         pinctrl-names = "default";
  59         pinctrl-0 = <&pinctrl_hog_base &pinctrl_hog>;
  60
  61         pinctrl_hog: hog-grp {
  62                 fsl,pins = <
  63                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x400120b0
  64                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x400120b0
  65                         MX6QDL_PAD_GPIO_5__GPIO1_IO05           0x400120b0
  66                         MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03       0x400120b0
  67                         MX6QDL_PAD_GPIO_19__GPIO4_IO05          0x120b0
  68                         MX6QDL_PAD_DI0_PIN4__GPIO4_IO20         0x400120b0
  69                         MX6QDL_PAD_EIM_D27__GPIO3_IO27          0x120b0
  70                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x120b0
  71                         MX6QDL_PAD_KEY_COL1__GPIO4_IO08         0x400120b0
  72                         MX6QDL_PAD_NANDF_CS1__GPIO6_IO14        0x400120b0
  73                         MX6QDL_PAD_NANDF_CS2__GPIO6_IO15        0x400120b0
  74                         MX6QDL_PAD_KEY_ROW1__GPIO4_IO09         0x400120b0
  75                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x400120b0
  76                         MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x400120b0
  77                         MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21       0x400120b0
  78                         MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x400120b0
  79                         MX6QDL_PAD_SD1_CMD__GPIO1_IO18          0x400120b0
  80                         MX6QDL_PAD_SD1_DAT0__GPIO1_IO16         0x400120b0
  81                         MX6QDL_PAD_SD1_DAT1__GPIO1_IO17         0x400120b0
  82                         MX6QDL_PAD_SD1_DAT2__GPIO1_IO19         0x400120b0
  83                         MX6QDL_PAD_SD1_CLK__GPIO1_IO20          0x400120b0
  84                         MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18      0x400120b0
  85                         MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19        0x400120b0
  86                         MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x400120b0
  87                 >;
  88         };
  89
  90         pinctrl_audmux_ext: audmux-ext-grp {
  91                 fsl,pins = <
  92                         MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
  93                         MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
  94                         MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
  95                         MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
  96                 >;
  97         };
  98
  99         pinctrl_enet_1G: enet-1G-grp {
 100                 fsl,pins = <
 101                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x100b0
 102                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x100b0
 103                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x100b0
 104                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x100b0
 105                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x100b0
 106                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x100b0
 107                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x100b0
 108                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x100b0
 109                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x100b0
 110                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 111                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 112                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 113                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 114                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 115                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 116                         MX6QDL_PAD_EIM_D29__GPIO3_IO29          0x000b0
 117                         MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x000b1
 118                         MX6QDL_PAD_EIM_D26__GPIO3_IO26          0x000b1
 119                 >;
 120         };
 121
 122         pinctrl_pcie: pcie-grp {
 123                 fsl,pins = <
 124                         MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20     0x1b0b1
 125                 >;
 126         };
 127 };
 128
 129 &pcie {
 130         pinctrl-names = "default";
 131         pinctrl-0 = <&pinctrl_pcie>;
 132         reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>;
 133         status = "okay";
 134 };
 135
 136 &ssi1 {
 137         status = "okay";
 138 };
 139
 140 &usdhc3 {
 141         status = "okay";
 142 };