1 // SPDX-License-Identifier: (GPL-2.0)
3 * support for the imx6 based aristainetos2c-cslb board
5 * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
6 * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/clock/imx6qdl-clock.h>
12 #include "imx6qdl-aristainetos2-common.dtsi"
16 compatible = "gpio-leds";
17 pinctrl-names = "default";
18 pinctrl-0 = <&pinctrl_gpio>;
22 gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
27 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
32 gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
37 gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
42 gpios = <&expander 15 GPIO_ACTIVE_LOW>;
43 default-state = "off";
48 gpios = <&expander 14 GPIO_ACTIVE_LOW>;
49 default-state = "off";
54 gpios = <&expander 12 GPIO_ACTIVE_LOW>;
55 default-state = "off";
59 label = "led_yellow2";
60 gpios = <&expander 13 GPIO_ACTIVE_LOW>;
61 default-state = "off";
66 gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
72 fsl,spi-num-chipselects = <3>;
73 cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH
74 &gpio4 10 GPIO_ACTIVE_HIGH
75 &gpio4 11 GPIO_ACTIVE_HIGH>;
76 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_ecspi1>;
79 pinctrl-assert-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
80 pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
85 compatible = "micron,n25q128a11", "jedec,spi-nor";
86 spi-max-frequency = <20000000>;
92 fsl,spi-num-chipselects = <2>;
93 cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>;
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_ecspi4>;
101 compatible = "infineon,slb9645tt";
110 gpios = <8 GPIO_ACTIVE_HIGH>;
115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_usdhc1>;
117 cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_usdhc2>;
131 pinctrl_ecspi1: ecspi1grp {
133 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
134 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
135 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
137 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1
139 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1
141 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1
142 /* WP pin NOR Flash */
143 MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0
145 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0
149 pinctrl_ecspi4: ecspi4grp {
151 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
152 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
153 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
154 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */
155 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */
159 pinctrl_gpio: gpiogrp {
162 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0
163 /* LCD power enable */
164 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0
166 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0
168 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x4001b0b0
170 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0
172 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0
174 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
175 /* FPGA IRQ currently unused*/
176 MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0
177 /* Display reset because of clock failure */
178 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0
179 /* spi bus #2 SS driver enable */
180 MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0
181 /* RST_LOC# PHY reset input (has pull-down!)*/
182 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0
183 /* Touchscreen IRQ */
184 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0
186 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0
187 /* make sure pin is GPIO and not ENET_REF_CLK */
188 MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001a0b0
190 MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x4001b0b0
192 MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0
194 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0
198 pinctrl_usbotg: usbotggrp {
200 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
201 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
205 pinctrl_usdhc1: usdhc1grp {
207 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
208 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
209 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
210 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
211 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
212 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
213 /* SD1 card detect input */
214 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0
218 pinctrl_usdhc2: usdhc2grp {
220 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
221 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
222 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
223 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
224 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
225 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
226 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
227 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
228 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
229 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059