arch/arm/dts/imx6qdl-aristainetos2.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0)
   2 /*
   3  * support for the imx6 based aristainetos2 board
   4  *
   5  * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
   6  * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
   7  *
   8  */
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/clock/imx6qdl-clock.h>
  11
  12 #include "imx6qdl-aristainetos2-common.dtsi"
  13
  14 / {
  15         leds {
  16                 compatible = "gpio-leds";
  17                 pinctrl-names = "default";
  18                 pinctrl-0 = <&pinctrl_gpio>;
  19
  20                 LED_blue {
  21                         label = "led_blue";
  22                         gpios = <&gpio2 29 GPIO_ACTIVE_LOW>;
  23                 };
  24
  25                 LED_green {
  26                         label = "led_green";
  27                         gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
  28                 };
  29
  30                 LED_red {
  31                         label = "led_red";
  32                         gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
  33                 };
  34
  35                 LED_yellow {
  36                         label = "led_yellow";
  37                         gpios = <&gpio6 16 GPIO_ACTIVE_LOW>;
  38                 };
  39
  40                 LED_ena {
  41                         label = "led_ena";
  42                         gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
  43                 };
  44         };
  45 };
  46
  47 &ecspi1 {
  48         fsl,spi-num-chipselects = <3>;
  49         cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH
  50                     &gpio4 10 GPIO_ACTIVE_HIGH
  51                     &gpio4 11 GPIO_ACTIVE_HIGH>;
  52         pinctrl-names = "default";
  53         pinctrl-0 = <&pinctrl_ecspi1>;
  54         status = "okay";
  55 };
  56
  57 &ecspi4 {
  58         fsl,spi-num-chipselects = <2>;
  59         cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>;
  60         pinctrl-names = "default";
  61         pinctrl-0 = <&pinctrl_ecspi4>;
  62         status = "okay";
  63         pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
  64
  65         flash: m25p80@1 {
  66                 #address-cells = <1>;
  67                 #size-cells = <1>;
  68                 compatible = "micron,n25q128a11", "jedec,spi-nor";
  69                 spi-max-frequency = <20000000>;
  70                 reg = <1>;
  71         };
  72 };
  73
  74 &gpio7 {
  75         sd2_driver_ena {
  76                 gpio-hog;
  77                 output-high;
  78                 gpios = <8 GPIO_ACTIVE_HIGH>;
  79         };
  80 };
  81
  82 &gpmi {
  83         pinctrl-names = "default";
  84         pinctrl-0 = <&pinctrl_gpmi_nand>;
  85         status = "okay";
  86 };
  87
  88 &can1 {
  89         pinctrl-names = "default";
  90         pinctrl-0 = <&pinctrl_flexcan1>;
  91         status = "okay";
  92 };
  93
  94 &can2 {
  95         pinctrl-names = "default";
  96         pinctrl-0 = <&pinctrl_flexcan2>;
  97         status = "okay";
  98 };
  99
 100 &usdhc1 {
 101         pinctrl-names = "default";
 102         pinctrl-0 = <&pinctrl_usdhc1>;
 103         cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
 104         no-1-8-v;
 105         status = "okay";
 106 };
 107
 108 &usdhc2 {
 109         pinctrl-names = "default";
 110         pinctrl-0 = <&pinctrl_usdhc2>;
 111         cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
 112         wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
 113         no-1-8-v;
 114         status = "okay";
 115 };
 116
 117 &iomuxc {
 118         pinctrl_ecspi1: ecspi1grp {
 119                 fsl,pins = <
 120                         MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
 121                         MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
 122                         MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
 123                         MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x100b1 /* SS0# */
 124                         MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 /* SS1# */
 125                         MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 /* SS2# */
 126                 >;
 127         };
 128
 129         pinctrl_ecspi4: ecspi4grp {
 130                 fsl,pins = <
 131                         MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
 132                         MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
 133                         MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
 134                         MX6QDL_PAD_EIM_D29__GPIO3_IO29  0x100b1 /* SS0# */
 135                         MX6QDL_PAD_EIM_A25__GPIO5_IO02  0x100b1 /* SS1# */
 136                         MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0 /* WP pin */
 137                 >;
 138         };
 139
 140         pinctrl_gpio: gpiogrp {
 141                 fsl,pins = <
 142                         /* led enable */
 143                         MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25      0x4001b0b0
 144                         /* LCD power enable */
 145                         MX6QDL_PAD_NANDF_CS2__GPIO6_IO15        0x4001b0b0
 146                         /* led yellow */
 147                         MX6QDL_PAD_NANDF_CS3__GPIO6_IO16        0x4001b0b0
 148                         /* led red */
 149                         MX6QDL_PAD_EIM_EB0__GPIO2_IO28          0x4001b0b0
 150                         /* led green */
 151                         MX6QDL_PAD_EIM_A24__GPIO5_IO04          0x4001b0b0
 152                         /* led blue */
 153                         MX6QDL_PAD_EIM_EB1__GPIO2_IO29          0x4001b0b0
 154                         /* Profibus IRQ */
 155                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x1b0b0
 156                         /* FPGA IRQ currently unused*/
 157                         MX6QDL_PAD_SD3_DAT6__GPIO6_IO18         0x1b0b0
 158                         /* Display reset because of clock failure */
 159                         MX6QDL_PAD_SD4_DAT3__GPIO2_IO11         0x4001b0b0
 160                         /* spi bus #2 SS driver enable */
 161                         MX6QDL_PAD_EIM_A23__GPIO6_IO06          0x4001b0b0
 162                         /* RST_LOC# PHY reset input (has pull-down!)*/
 163                         MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x4001b0b0
 164                         /* USB_OTG_ID = GPIO1_24*/
 165                         MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x4001b0b0
 166                         /* Touchscreen IRQ */
 167                         MX6QDL_PAD_SD4_DAT1__GPIO2_IO09         0x1b0b0
 168                         /* PCIe reset */
 169                         MX6QDL_PAD_EIM_A22__GPIO2_IO16          0x4001b0b0
 170                 >;
 171         };
 172
 173         pinctrl_gpmi_nand: gpmi-nand {
 174                 fsl,pins = <
 175                         MX6QDL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
 176                         MX6QDL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
 177                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
 178                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
 179                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
 180                         MX6QDL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
 181                         MX6QDL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
 182                         MX6QDL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
 183                         MX6QDL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
 184                         MX6QDL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
 185                         MX6QDL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
 186                         MX6QDL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
 187                         MX6QDL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
 188                         MX6QDL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
 189                         MX6QDL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
 190                 >;
 191         };
 192
 193         pinctrl_flexcan1: flexcan1grp {
 194                 fsl,pins = <
 195                         MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0
 196                         MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0
 197                 >;
 198         };
 199
 200         pinctrl_flexcan2: flexcan2grp {
 201                 fsl,pins = <
 202                         MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0
 203                         MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0
 204                 >;
 205         };
 206
 207         pinctrl_usbotg: usbotggrp {
 208                 fsl,pins = <
 209                         MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
 210                 >;
 211         };
 212
 213         pinctrl_usdhc1: usdhc1grp {
 214                 fsl,pins = <
 215                         MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17059
 216                         MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10059
 217                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
 218                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
 219                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
 220                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
 221                         /* SD1 card detect input */
 222                         MX6QDL_PAD_ENET_RXD0__GPIO1_IO27        0x1b0b0
 223                         /* SD1 write protect input */
 224                         MX6QDL_PAD_DI0_PIN4__GPIO4_IO20         0x1b0b0
 225                 >;
 226         };
 227
 228         pinctrl_usdhc2: usdhc2grp {
 229                 fsl,pins = <
 230                         MX6QDL_PAD_SD2_CMD__SD2_CMD    0x71
 231                         MX6QDL_PAD_SD2_CLK__SD2_CLK    0x71
 232                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71
 233                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71
 234                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71
 235                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71
 236                         /* SD2 level shifter output enable */
 237                         MX6QDL_PAD_SD3_RST__GPIO7_IO08          0x4001b0b0
 238                         /* SD2 card detect input */
 239                         MX6QDL_PAD_GPIO_19__GPIO4_IO05          0x1b0b0
 240                         /* SD2 write protect input */
 241                         MX6QDL_PAD_SD4_DAT2__GPIO2_IO10         0x1b0b0
 242                 >;
 243         };
 244 };