arch/arm/dts/imx6q-ba16.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * Support for imx6 based Advantech DMS-BA16 Qseven module
   4  *
   5  * Copyright 2015 Timesys Corporation.
   6  * Copyright 2015 General Electric Company
   7  *
   8  * This file is dual-licensed: you can use it either under the terms
   9  * of the GPL or the X11 license, at your option. Note that this dual
  10  * licensing only applies to this file, and not this project as a
  11  * whole.
  12  *
  13  *  a) This file is free software; you can redistribute it and/or
  14  *     modify it under the terms of the GNU General Public License
  15  *     version 2 as published by the Free Software Foundation.
  16  *
  17  *     This file is distributed in the hope that it will be useful,
  18  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *     GNU General Public License for more details.
  21  *
  22  * Or, alternatively,
  23  *
  24  *  b) Permission is hereby granted, free of charge, to any person
  25  *     obtaining a copy of this software and associated documentation
  26  *     files (the "Software"), to deal in the Software without
  27  *     restriction, including without limitation the rights to use,
  28  *     copy, modify, merge, publish, distribute, sublicense, and/or
  29  *     sell copies of the Software, and to permit persons to whom the
  30  *     Software is furnished to do so, subject to the following
  31  *     conditions:
  32  *
  33  *     The above copyright notice and this permission notice shall be
  34  *     included in all copies or substantial portions of the Software.
  35  *
  36  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  37  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  38  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  39  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  40  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  41  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  42  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  43  *     OTHER DEALINGS IN THE SOFTWARE.
  44  */
  45
  46 #include "imx6q.dtsi"
  47 #include <dt-bindings/gpio/gpio.h>
  48
  49 / {
  50         memory@10000000 {
  51                 device_type = "memory";
  52                 reg = <0x10000000 0x40000000>;
  53         };
  54
  55         backlight_lvds: backlight {
  56                 compatible = "pwm-backlight";
  57                 pinctrl-names = "default";
  58                 pinctrl-0 = <&pinctrl_display>;
  59                 pwms = <&pwm1 0 5000000>;
  60                 brightness-levels = <  0   1   2   3   4   5   6   7   8   9
  61                                       10  11  12  13  14  15  16  17  18  19
  62                                       20  21  22  23  24  25  26  27  28  29
  63                                       30  31  32  33  34  35  36  37  38  39
  64                                       40  41  42  43  44  45  46  47  48  49
  65                                       50  51  52  53  54  55  56  57  58  59
  66                                       60  61  62  63  64  65  66  67  68  69
  67                                       70  71  72  73  74  75  76  77  78  79
  68                                       80  81  82  83  84  85  86  87  88  89
  69                                       90  91  92  93  94  95  96  97  98  99
  70                                      100 101 102 103 104 105 106 107 108 109
  71                                      110 111 112 113 114 115 116 117 118 119
  72                                      120 121 122 123 124 125 126 127 128 129
  73                                      130 131 132 133 134 135 136 137 138 139
  74                                      140 141 142 143 144 145 146 147 148 149
  75                                      150 151 152 153 154 155 156 157 158 159
  76                                      160 161 162 163 164 165 166 167 168 169
  77                                      170 171 172 173 174 175 176 177 178 179
  78                                      180 181 182 183 184 185 186 187 188 189
  79                                      190 191 192 193 194 195 196 197 198 199
  80                                      200 201 202 203 204 205 206 207 208 209
  81                                      210 211 212 213 214 215 216 217 218 219
  82                                      220 221 222 223 224 225 226 227 228 229
  83                                      230 231 232 233 234 235 236 237 238 239
  84                                      240 241 242 243 244 245 246 247 248 249
  85                                      250 251 252 253 254 255>;
  86                 default-brightness-level = <255>;
  87                 enable-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
  88         };
  89
  90         reg_1p8v: regulator-1p8v {
  91                 compatible = "regulator-fixed";
  92                 regulator-name = "1P8V";
  93                 regulator-min-microvolt = <1800000>;
  94                 regulator-max-microvolt = <1800000>;
  95                 regulator-always-on;
  96         };
  97
  98         reg_3p3v: regulator-3p3v {
  99                 compatible = "regulator-fixed";
 100                 regulator-name = "3P3V";
 101                 regulator-min-microvolt = <3300000>;
 102                 regulator-max-microvolt = <3300000>;
 103                 regulator-always-on;
 104         };
 105
 106         reg_lvds: regulator-lvds {
 107                 compatible = "regulator-fixed";
 108                 regulator-name = "lvds_ppen";
 109                 regulator-min-microvolt = <3300000>;
 110                 regulator-max-microvolt = <3300000>;
 111                 regulator-boot-on;
 112                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 113                 enable-active-high;
 114         };
 115
 116         reg_usb_h1_vbus: regulator-usbh1vbus {
 117                 compatible = "regulator-fixed";
 118                 regulator-name = "usb_h1_vbus";
 119                 regulator-min-microvolt = <5000000>;
 120                 regulator-max-microvolt = <5000000>;
 121         };
 122
 123         reg_usb_otg_vbus: regulator-usbotgvbus {
 124                 compatible = "regulator-fixed";
 125                 regulator-name = "usb_otg_vbus";
 126                 regulator-min-microvolt = <5000000>;
 127                 regulator-max-microvolt = <5000000>;
 128         };
 129 };
 130
 131 &audmux {
 132         pinctrl-names = "default";
 133         pinctrl-0 = <&pinctrl_audmux>;
 134         status = "okay";
 135 };
 136
 137 &ecspi1 {
 138         cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
 139         pinctrl-names = "default";
 140         pinctrl-0 = <&pinctrl_ecspi1>;
 141         status = "okay";
 142
 143         flash: n25q032@0 {
 144                 compatible = "jedec,spi-nor";
 145                 #address-cells = <1>;
 146                 #size-cells = <1>;
 147                 spi-max-frequency = <20000000>;
 148                 reg = <0>;
 149
 150                 partition@0 {
 151                         label = "U-Boot";
 152                         reg = <0x0 0xc0000>;
 153                 };
 154
 155                 partition@c0000 {
 156                         label = "env";
 157                         reg = <0xc0000 0x10000>;
 158                 };
 159
 160                 partition@d0000 {
 161                         label = "spare";
 162                         reg = <0xd0000 0x320000>;
 163                 };
 164
 165                 partition@3f0000 {
 166                         label = "mfg";
 167                         reg = <0x3f0000 0x10000>;
 168                 };
 169         };
 170 };
 171
 172 &fec {
 173         pinctrl-names = "default";
 174         pinctrl-0 = <&pinctrl_enet>;
 175         phy-mode = "rgmii-id";
 176         status = "okay";
 177         phy-handle = <&phy0>;
 178
 179         mdio {
 180                 #address-cells = <1>;
 181                 #size-cells = <0>;
 182
 183                 phy0: ethernet-phy@4 {
 184                         reg = <4>;
 185                         qca,clk-out-frequency = <125000000>;
 186                 };
 187         };
 188 };
 189
 190 &hdmi {
 191         ddc-i2c-bus = <&i2c2>;
 192         status = "okay";
 193 };
 194
 195 &i2c1 {
 196         clock-frequency = <100000>;
 197         pinctrl-names = "default";
 198         pinctrl-0 = <&pinctrl_i2c1>;
 199         status = "okay";
 200 };
 201
 202 &i2c2 {
 203         clock-frequency = <100000>;
 204         pinctrl-names = "default";
 205         pinctrl-0 = <&pinctrl_i2c2>;
 206         status = "okay";
 207 };
 208
 209 &i2c3 {
 210         clock-frequency = <100000>;
 211         pinctrl-names = "default";
 212         pinctrl-0 = <&pinctrl_i2c3>;
 213         status = "okay";
 214
 215         pmic@58 {
 216                 compatible = "dlg,da9063";
 217                 reg = <0x58>;
 218                 pinctrl-names = "default";
 219                 pinctrl-0 = <&pinctrl_pmic>;
 220                 interrupt-parent = <&gpio7>;
 221                 interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
 222
 223                 onkey {
 224                         compatible = "dlg,da9063-onkey";
 225                 };
 226
 227                 regulators {
 228                         vdd_bcore1: bcore1 {
 229                                 regulator-min-microvolt = <1420000>;
 230                                 regulator-max-microvolt = <1420000>;
 231                                 regulator-always-on;
 232                                 regulator-boot-on;
 233                         };
 234
 235                         vdd_bcore2: bcore2 {
 236                                 regulator-min-microvolt = <1420000>;
 237                                 regulator-max-microvolt = <1420000>;
 238                                 regulator-always-on;
 239                                 regulator-boot-on;
 240                         };
 241
 242                         vdd_bpro: bpro {
 243                                 regulator-min-microvolt = <1500000>;
 244                                 regulator-max-microvolt = <1500000>;
 245                                 regulator-always-on;
 246                                 regulator-boot-on;
 247                         };
 248
 249                         vdd_bmem: bmem {
 250                                 regulator-min-microvolt = <1800000>;
 251                                 regulator-max-microvolt = <1800000>;
 252                                 regulator-always-on;
 253                                 regulator-boot-on;
 254                         };
 255
 256                         vdd_bio: bio {
 257                                 regulator-min-microvolt = <1800000>;
 258                                 regulator-max-microvolt = <1800000>;
 259                                 regulator-always-on;
 260                                 regulator-boot-on;
 261                         };
 262
 263                         vdd_bperi: bperi {
 264                                 regulator-min-microvolt = <3300000>;
 265                                 regulator-max-microvolt = <3300000>;
 266                                 regulator-always-on;
 267                                 regulator-boot-on;
 268                         };
 269
 270                         vdd_ldo1: ldo1 {
 271                                 regulator-min-microvolt = <600000>;
 272                                 regulator-max-microvolt = <1860000>;
 273                         };
 274
 275                         vdd_ldo2: ldo2 {
 276                                 regulator-min-microvolt = <600000>;
 277                                 regulator-max-microvolt = <1860000>;
 278                         };
 279
 280                         vdd_ldo3: ldo3 {
 281                                 regulator-min-microvolt = <900000>;
 282                                 regulator-max-microvolt = <3440000>;
 283                         };
 284
 285                         vdd_ldo4: ldo4 {
 286                                 regulator-min-microvolt = <900000>;
 287                                 regulator-max-microvolt = <3440000>;
 288                         };
 289
 290                         vdd_ldo5: ldo5 {
 291                                 regulator-min-microvolt = <900000>;
 292                                 regulator-max-microvolt = <3600000>;
 293                         };
 294
 295                         vdd_ldo6: ldo6 {
 296                                 regulator-min-microvolt = <900000>;
 297                                 regulator-max-microvolt = <3600000>;
 298                         };
 299
 300                         vdd_ldo7: ldo7 {
 301                                 regulator-min-microvolt = <900000>;
 302                                 regulator-max-microvolt = <3600000>;
 303                         };
 304
 305                         vdd_ldo8: ldo8 {
 306                                 regulator-min-microvolt = <900000>;
 307                                 regulator-max-microvolt = <3600000>;
 308                         };
 309
 310                         vdd_ldo9: ldo9 {
 311                                 regulator-min-microvolt = <950000>;
 312                                 regulator-max-microvolt = <3600000>;
 313                         };
 314
 315                         vdd_ldo10: ldo10 {
 316                                 regulator-min-microvolt = <900000>;
 317                                 regulator-max-microvolt = <3600000>;
 318                         };
 319
 320                         vdd_ldo11: ldo11 {
 321                                 regulator-min-microvolt = <900000>;
 322                                 regulator-max-microvolt = <3600000>;
 323                                 regulator-always-on;
 324                                 regulator-boot-on;
 325                         };
 326                 };
 327         };
 328
 329         rtc@32 {
 330                 compatible = "epson,rx8010";
 331                 pinctrl-names = "default";
 332                 pinctrl-0 = <&pinctrl_rtc>;
 333                 reg = <0x32>;
 334                 interrupt-parent = <&gpio4>;
 335                 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
 336         };
 337 };
 338
 339 &pcie {
 340         pinctrl-names = "default";
 341         pinctrl-0 = <&pinctrl_pcie>;
 342         reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
 343         fsl,tx-swing-full = <103>;
 344         fsl,tx-swing-low = <103>;
 345         status = "okay";
 346 };
 347
 348 &pwm1 {
 349         pinctrl-names = "default";
 350         pinctrl-0 = <&pinctrl_pwm1>;
 351         status = "okay";
 352 };
 353
 354 &pwm2 {
 355         pinctrl-names = "default";
 356         pinctrl-0 = <&pinctrl_pwm2>;
 357         status = "disabled";
 358 };
 359
 360 &sata {
 361         status = "okay";
 362 };
 363
 364 &ssi1 {
 365         status = "okay";
 366 };
 367
 368 &uart3 {
 369         pinctrl-names = "default";
 370         pinctrl-0 = <&pinctrl_uart3>;
 371         uart-has-rtscts;
 372         status = "okay";
 373 };
 374
 375 &uart4 {
 376         pinctrl-names = "default";
 377         pinctrl-0 = <&pinctrl_uart4>;
 378         status = "okay";
 379 };
 380
 381 &usbh1 {
 382         pinctrl-names = "default";
 383         pinctrl-0 = <&pinctrl_usbhub>;
 384         vbus-supply = <&reg_usb_h1_vbus>;
 385         reset-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
 386         status = "okay";
 387 };
 388
 389 &usbotg {
 390         vbus-supply = <&reg_usb_otg_vbus>;
 391         pinctrl-names = "default";
 392         pinctrl-0 = <&pinctrl_usbotg>;
 393         disable-over-current;
 394         status = "okay";
 395 };
 396
 397 &usdhc2 {
 398         pinctrl-names = "default";
 399         pinctrl-0 = <&pinctrl_usdhc2>;
 400         cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
 401         no-1-8-v;
 402         keep-power-in-suspend;
 403         wakeup-source;
 404         status = "okay";
 405 };
 406
 407 &usdhc3 {
 408         pinctrl-names = "default";
 409         pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_reset>;
 410         bus-width = <8>;
 411         vmmc-supply = <&vdd_bperi>;
 412         non-removable;
 413         keep-power-in-suspend;
 414         status = "okay";
 415 };
 416
 417 &wdog1 {
 418         pinctrl-names = "default";
 419         pinctrl-0 = <&pinctrl_wdog>;
 420         fsl,ext-reset-output;
 421 };
 422
 423 &iomuxc {
 424         pinctrl-names = "default";
 425         pinctrl-0 = <&pinctrl_hog>;
 426
 427         pinctrl_audmux: audmuxgrp {
 428                 fsl,pins = <
 429                         MX6QDL_PAD_DISP0_DAT20__AUD4_TXC  0x130b0
 430                         MX6QDL_PAD_DISP0_DAT21__AUD4_TXD  0x130b0
 431                         MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
 432                         MX6QDL_PAD_DISP0_DAT23__AUD4_RXD  0x130b0
 433                 >;
 434         };
 435
 436         pinctrl_display: dispgrp {
 437                 fsl,pins = <
 438                         /* BLEN_OUT */
 439                         MX6QDL_PAD_GPIO_0__GPIO1_IO00    0x1b0b0
 440                         /* LVDS_PPEN_OUT */
 441                         MX6QDL_PAD_EIM_D22__GPIO3_IO22   0x1b0b0
 442                 >;
 443         };
 444
 445         pinctrl_ecspi1: ecspi1grp {
 446                 fsl,pins = <
 447                         MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
 448                         MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
 449                         MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
 450                         /* SPI1 CS */
 451                         MX6QDL_PAD_EIM_EB2__GPIO2_IO30  0x1b0b0
 452                 >;
 453         };
 454
 455         pinctrl_ecspi5: ecspi5grp {
 456                 fsl,pins = <
 457                         MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO        0x1b0b0
 458                         MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI         0x1b0b0
 459                         MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK         0x1b0b0
 460                         MX6QDL_PAD_SD1_DAT1__GPIO1_IO17         0x1b0b0
 461                 >;
 462         };
 463
 464         pinctrl_enet: enetgrp {
 465                 fsl,pins = <
 466                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x100b0
 467                         MX6QDL_PAD_ENET_MDC__ENET_MDC         0x100b0
 468                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x10030
 469                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x10030
 470                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x10030
 471                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x10030
 472                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x10030
 473                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
 474                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x100b0
 475                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b030
 476                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b030
 477                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b030
 478                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b030
 479                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b030
 480                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
 481                         /* FEC Reset */
 482                         MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28     0x1b0b0
 483                         /* AR8033 Interrupt */
 484                         MX6QDL_PAD_GPIO_19__GPIO4_IO05        0x1b0b0
 485                 >;
 486         };
 487
 488         pinctrl_hog: hoggrp {
 489                 fsl,pins = <
 490                         /* GPIO 0-7 */
 491                         MX6QDL_PAD_NANDF_D0__GPIO2_IO00  0x1b0b0
 492                         MX6QDL_PAD_NANDF_D1__GPIO2_IO01  0x1b0b0
 493                         MX6QDL_PAD_NANDF_D2__GPIO2_IO02  0x1b0b0
 494                         MX6QDL_PAD_NANDF_D3__GPIO2_IO03  0x1b0b0
 495                         MX6QDL_PAD_NANDF_D4__GPIO2_IO04  0x1b0b0
 496                         MX6QDL_PAD_NANDF_D5__GPIO2_IO05  0x1b0b0
 497                         MX6QDL_PAD_NANDF_D6__GPIO2_IO06  0x1b0b0
 498                         MX6QDL_PAD_NANDF_D7__GPIO2_IO07  0x1b0b0
 499                         /* SUS_S3_OUT to CPLD */
 500                         MX6QDL_PAD_KEY_ROW2__GPIO4_IO11  0x1b0b0
 501                 >;
 502         };
 503
 504         pinctrl_i2c1: i2c1grp {
 505                 fsl,pins = <
 506                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA  0x4001b8b1
 507                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL  0x4001b8b1
 508                 >;
 509         };
 510
 511         pinctrl_i2c2: i2c2grp {
 512                 fsl,pins = <
 513                         MX6QDL_PAD_KEY_COL3__I2C2_SCL   0x4001b8b1
 514                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA   0x4001b8b1
 515                 >;
 516         };
 517
 518         pinctrl_i2c3: i2c3grp {
 519                 fsl,pins = <
 520                         MX6QDL_PAD_GPIO_3__I2C3_SCL     0x4001b8b1
 521                         MX6QDL_PAD_GPIO_6__I2C3_SDA     0x4001b8b1
 522                 >;
 523         };
 524
 525         pinctrl_pcie: pciegrp {
 526                 fsl,pins = <
 527                         /* PCIe Reset */
 528                         MX6QDL_PAD_GPIO_17__GPIO7_IO12  0x1b0b0
 529                         /* PCIe Wake */
 530                         MX6QDL_PAD_GPIO_5__GPIO1_IO05   0x1b0b0
 531                 >;
 532         };
 533
 534         pinctrl_pmic: pmicgrp {
 535                 fsl,pins = <
 536                         /* PMIC Interrupt */
 537                         MX6QDL_PAD_GPIO_18__GPIO7_IO13  0x1b0b0
 538                 >;
 539         };
 540
 541         pinctrl_pwm1: pwm1grp {
 542                 fsl,pins = <
 543                         MX6QDL_PAD_SD1_DAT3__PWM1_OUT   0x1b0b1
 544                 >;
 545         };
 546
 547         pinctrl_pwm2: pwm2grp {
 548                 fsl,pins = <
 549                         MX6QDL_PAD_GPIO_1__PWM2_OUT     0x1b0b1
 550                 >;
 551         };
 552
 553         pinctrl_rtc: rtcgrp {
 554                 fsl,pins = <
 555                         /* RTC_INT */
 556                         MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
 557                 >;
 558         };
 559
 560         pinctrl_uart3: uart3grp {
 561                 fsl,pins = <
 562                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
 563                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
 564                         MX6QDL_PAD_EIM_D23__UART3_CTS_B   0x1b0b1
 565                         MX6QDL_PAD_EIM_D31__UART3_RTS_B   0x1b0b1
 566                 >;
 567         };
 568
 569         pinctrl_uart4: uart4grp {
 570                 fsl,pins = <
 571                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
 572                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
 573                 >;
 574         };
 575
 576         pinctrl_usbhub: usbhubgrp {
 577                 fsl,pins = <
 578                         /* HUB_RESET */
 579                         MX6QDL_PAD_GPIO_16__GPIO7_IO11  0x1b0b0
 580                 >;
 581         };
 582
 583         pinctrl_usbotg: usbotggrp {
 584                 fsl,pins = <
 585                         MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
 586                 >;
 587         };
 588
 589         pinctrl_usdhc2: usdhc2grp {
 590                 fsl,pins = <
 591                         MX6QDL_PAD_SD2_CMD__SD2_CMD     0x17059
 592                         MX6QDL_PAD_SD2_CLK__SD2_CLK     0x10059
 593                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0  0x17059
 594                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1  0x17059
 595                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2  0x17059
 596                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3  0x17059
 597                         /* uSDHC2 CD */
 598                         MX6QDL_PAD_GPIO_4__GPIO1_IO04   0x1b0b0
 599                 >;
 600         };
 601
 602         pinctrl_usdhc3: usdhc3grp {
 603                 fsl,pins = <
 604                         MX6QDL_PAD_SD3_CMD__SD3_CMD     0x17059
 605                         MX6QDL_PAD_SD3_CLK__SD3_CLK     0x10059
 606                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0  0x17059
 607                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1  0x17059
 608                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2  0x17059
 609                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3  0x17059
 610                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4  0x17059
 611                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5  0x17059
 612                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6  0x17059
 613                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7  0x17059
 614                 >;
 615         };
 616
 617         pinctrl_usdhc3_reset: usdhc3grp-reset {
 618                 fsl,pins = <
 619                         MX6QDL_PAD_SD3_RST__SD3_RESET   0x170F9
 620                 >;
 621         };
 622
 623         pinctrl_usdhc4: usdhc4grp {
 624                 fsl,pins = <
 625                         MX6QDL_PAD_SD4_CMD__SD4_CMD     0x17059
 626                         MX6QDL_PAD_SD4_CLK__SD4_CLK     0x17059
 627                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0  0x17059
 628                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1  0x17059
 629                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2  0x17059
 630                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3  0x17059
 631                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4  0x17059
 632                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5  0x17059
 633                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6  0x17059
 634                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7  0x17059
 635                         /* uSDHC4 CD */
 636                         MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0
 637                         /* uSDHC4 SDIO PWR */
 638                         MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
 639                         /* uSDHC4 SDIO WP */
 640                         MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0
 641                         /* uSDHC4 SDIO LED */
 642                         MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0
 643                 >;
 644         };
 645
 646         pinctrl_wdog: wdoggrp {
 647                 fsl,pins = <
 648                         MX6QDL_PAD_GPIO_9__WDOG1_B      0x1b0b0
 649                 >;
 650         };
 651 };