ARM: dts: k3-j7200-r5-common-proc-board: Enable HyperFlash
[platform/kernel/u-boot.git] / arch / arm / dts / imx6dl.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Copyright 2013 Freescale Semiconductor, Inc.
4
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6dl-pinfunc.h"
7 #include "imx6qdl.dtsi"
8
9 / {
10         aliases {
11                 i2c3 = &i2c4;
12         };
13
14         cpus {
15                 #address-cells = <1>;
16                 #size-cells = <0>;
17
18                 cpu@0 {
19                         compatible = "arm,cortex-a9";
20                         device_type = "cpu";
21                         reg = <0>;
22                         next-level-cache = <&L2>;
23                         operating-points = <
24                                 /* kHz    uV */
25                                 996000  1250000
26                                 792000  1175000
27                                 396000  1150000
28                         >;
29                         fsl,soc-operating-points = <
30                                 /* ARM kHz  SOC-PU uV */
31                                 996000  1175000
32                                 792000  1175000
33                                 396000  1175000
34                         >;
35                         clock-latency = <61036>; /* two CLK32 periods */
36                         #cooling-cells = <2>;
37                         clocks = <&clks IMX6QDL_CLK_ARM>,
38                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
39                                  <&clks IMX6QDL_CLK_STEP>,
40                                  <&clks IMX6QDL_CLK_PLL1_SW>,
41                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
42                         clock-names = "arm", "pll2_pfd2_396m", "step",
43                                       "pll1_sw", "pll1_sys";
44                         arm-supply = <&reg_arm>;
45                         pu-supply = <&reg_pu>;
46                         soc-supply = <&reg_soc>;
47                 };
48
49                 cpu@1 {
50                         compatible = "arm,cortex-a9";
51                         device_type = "cpu";
52                         reg = <1>;
53                         next-level-cache = <&L2>;
54                         operating-points = <
55                                 /* kHz    uV */
56                                 996000  1250000
57                                 792000  1175000
58                                 396000  1150000
59                         >;
60                         fsl,soc-operating-points = <
61                                 /* ARM kHz  SOC-PU uV */
62                                 996000  1175000
63                                 792000  1175000
64                                 396000  1175000
65                         >;
66                         clock-latency = <61036>; /* two CLK32 periods */
67                         clocks = <&clks IMX6QDL_CLK_ARM>,
68                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
69                                  <&clks IMX6QDL_CLK_STEP>,
70                                  <&clks IMX6QDL_CLK_PLL1_SW>,
71                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
72                         clock-names = "arm", "pll2_pfd2_396m", "step",
73                                       "pll1_sw", "pll1_sys";
74                         arm-supply = <&reg_arm>;
75                         pu-supply = <&reg_pu>;
76                         soc-supply = <&reg_soc>;
77                 };
78         };
79
80         soc {
81                 ocram: sram@900000 {
82                         compatible = "mmio-sram";
83                         reg = <0x00900000 0x20000>;
84                         clocks = <&clks IMX6QDL_CLK_OCRAM>;
85                 };
86
87                 aips1: aips-bus@2000000 {
88                         iomuxc: iomuxc@20e0000 {
89                                 compatible = "fsl,imx6dl-iomuxc";
90                         };
91
92                         pxp: pxp@20f0000 {
93                                 reg = <0x020f0000 0x4000>;
94                                 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
95                         };
96
97                         epdc: epdc@20f4000 {
98                                 reg = <0x020f4000 0x4000>;
99                                 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
100                         };
101                 };
102
103                 aips2: aips-bus@2100000 {
104                         i2c4: i2c@21f8000 {
105                                 #address-cells = <1>;
106                                 #size-cells = <0>;
107                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
108                                 reg = <0x021f8000 0x4000>;
109                                 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
110                                 clocks = <&clks IMX6DL_CLK_I2C4>;
111                                 status = "disabled";
112                         };
113                 };
114         };
115
116         capture-subsystem {
117                 compatible = "fsl,imx-capture-subsystem";
118                 ports = <&ipu1_csi0>, <&ipu1_csi1>;
119         };
120
121         display-subsystem {
122                 compatible = "fsl,imx-display-subsystem";
123                 ports = <&ipu1_di0>, <&ipu1_di1>;
124         };
125 };
126
127 &gpio1 {
128         gpio-ranges = <&iomuxc  0 131 2>, <&iomuxc  2 137 8>, <&iomuxc 10 189 2>,
129                       <&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>,
130                       <&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184 1>,
131                       <&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188 1>,
132                       <&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127 1>,
133                       <&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130 1>,
134                       <&iomuxc 30 129 1>, <&iomuxc 31 122 1>;
135 };
136
137 &gpio2 {
138         gpio-ranges = <&iomuxc  0 161 8>, <&iomuxc  8 208 8>, <&iomuxc 16  74 1>,
139                       <&iomuxc 17  73 1>, <&iomuxc 18  72 1>, <&iomuxc 19  71 1>,
140                       <&iomuxc 20  70 1>, <&iomuxc 21  69 1>, <&iomuxc 22  68 1>,
141                       <&iomuxc 23  79 2>, <&iomuxc 25 118 2>, <&iomuxc 27 117 1>,
142                       <&iomuxc 28 113 4>;
143 };
144
145 &gpio3 {
146         gpio-ranges = <&iomuxc  0 97  2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>,
147                       <&iomuxc 16 81 16>;
148 };
149
150 &gpio4 {
151         gpio-ranges = <&iomuxc  5 136 1>, <&iomuxc  6 145 1>, <&iomuxc  7 150 1>,
152                       <&iomuxc  8 146 1>, <&iomuxc  9 151 1>, <&iomuxc 10 147 1>,
153                       <&iomuxc 11 152 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153 1>,
154                       <&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16  39 7>,
155                       <&iomuxc 23  56 1>, <&iomuxc 24  61 7>, <&iomuxc 31  46 1>;
156 };
157
158 &gpio5 {
159         gpio-ranges = <&iomuxc  0 120 1>, <&iomuxc  2 77 1>, <&iomuxc  4 76 1>,
160                       <&iomuxc  5  47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37 1>,
161                       <&iomuxc 19  36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38 1>,
162                       <&iomuxc 22  29 6>, <&iomuxc 28 19 4>;
163 };
164
165 &gpio6 {
166         gpio-ranges = <&iomuxc  0  23 6>, <&iomuxc  6  75 1>, <&iomuxc  7 156 1>,
167                       <&iomuxc  8 155 1>, <&iomuxc  9 170 1>, <&iomuxc 10 169 1>,
168                       <&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204 1>,
169                       <&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177 4>,
170                       <&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181 1>,
171                       <&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31  78 1>;
172 };
173
174 &gpio7 {
175         gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc  1 201 1>, <&iomuxc  2 196 1>,
176                       <&iomuxc 3 195 1>, <&iomuxc  4 197 4>, <&iomuxc  8 205 1>,
177                       <&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>;
178 };
179
180 &gpr {
181         ipu1_csi0_mux {
182                 compatible = "video-mux";
183                 mux-controls = <&mux 0>;
184                 #address-cells = <1>;
185                 #size-cells = <0>;
186
187                 port@0 {
188                         reg = <0>;
189
190                         ipu1_csi0_mux_from_mipi_vc0: endpoint {
191                                 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
192                         };
193                 };
194
195                 port@1 {
196                         reg = <1>;
197
198                         ipu1_csi0_mux_from_mipi_vc1: endpoint {
199                                 remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>;
200                         };
201                 };
202
203                 port@2 {
204                         reg = <2>;
205
206                         ipu1_csi0_mux_from_mipi_vc2: endpoint {
207                                 remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>;
208                         };
209                 };
210
211                 port@3 {
212                         reg = <3>;
213
214                         ipu1_csi0_mux_from_mipi_vc3: endpoint {
215                                 remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>;
216                         };
217                 };
218
219                 port@4 {
220                         reg = <4>;
221
222                         ipu1_csi0_mux_from_parallel_sensor: endpoint {
223                         };
224                 };
225
226                 port@5 {
227                         reg = <5>;
228
229                         ipu1_csi0_mux_to_ipu1_csi0: endpoint {
230                                 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
231                         };
232                 };
233         };
234
235         ipu1_csi1_mux {
236                 compatible = "video-mux";
237                 mux-controls = <&mux 1>;
238                 #address-cells = <1>;
239                 #size-cells = <0>;
240
241                 port@0 {
242                         reg = <0>;
243
244                         ipu1_csi1_mux_from_mipi_vc0: endpoint {
245                                 remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>;
246                         };
247                 };
248
249                 port@1 {
250                         reg = <1>;
251
252                         ipu1_csi1_mux_from_mipi_vc1: endpoint {
253                                 remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>;
254                         };
255                 };
256
257                 port@2 {
258                         reg = <2>;
259
260                         ipu1_csi1_mux_from_mipi_vc2: endpoint {
261                                 remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>;
262                         };
263                 };
264
265                 port@3 {
266                         reg = <3>;
267
268                         ipu1_csi1_mux_from_mipi_vc3: endpoint {
269                                 remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>;
270                         };
271                 };
272
273                 port@4 {
274                         reg = <4>;
275
276                         ipu1_csi1_mux_from_parallel_sensor: endpoint {
277                         };
278                 };
279
280                 port@5 {
281                         reg = <5>;
282
283                         ipu1_csi1_mux_to_ipu1_csi1: endpoint {
284                                 remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>;
285                         };
286                 };
287         };
288 };
289
290 &gpt {
291         compatible = "fsl,imx6dl-gpt";
292 };
293
294 &hdmi {
295         compatible = "fsl,imx6dl-hdmi";
296 };
297
298 &ipu1_csi1 {
299         ipu1_csi1_from_ipu1_csi1_mux: endpoint {
300                 remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
301         };
302 };
303
304 &ldb {
305         clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
306                  <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
307                  <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
308         clock-names = "di0_pll", "di1_pll",
309                       "di0_sel", "di1_sel",
310                       "di0", "di1";
311 };
312
313 &mipi_csi {
314         port@1 {
315                 reg = <1>;
316                 #address-cells = <1>;
317                 #size-cells = <0>;
318
319                 mipi_vc0_to_ipu1_csi0_mux: endpoint@0 {
320                         reg = <0>;
321                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
322                 };
323
324                 mipi_vc0_to_ipu1_csi1_mux: endpoint@1 {
325                         reg = <1>;
326                         remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;
327                 };
328         };
329
330         port@2 {
331                 reg = <2>;
332                 #address-cells = <1>;
333                 #size-cells = <0>;
334
335                 mipi_vc1_to_ipu1_csi0_mux: endpoint@0 {
336                         reg = <0>;
337                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>;
338                 };
339
340                 mipi_vc1_to_ipu1_csi1_mux: endpoint@1 {
341                         reg = <1>;
342                         remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>;
343                 };
344         };
345
346         port@3 {
347                 reg = <3>;
348                 #address-cells = <1>;
349                 #size-cells = <0>;
350
351                 mipi_vc2_to_ipu1_csi0_mux: endpoint@0 {
352                         reg = <0>;
353                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>;
354                 };
355
356                 mipi_vc2_to_ipu1_csi1_mux: endpoint@1 {
357                         reg = <1>;
358                         remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>;
359                 };
360         };
361
362         port@4 {
363                 reg = <4>;
364                 #address-cells = <1>;
365                 #size-cells = <0>;
366
367                 mipi_vc3_to_ipu1_csi0_mux: endpoint@0 {
368                         reg = <0>;
369                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>;
370                 };
371
372                 mipi_vc3_to_ipu1_csi1_mux: endpoint@1 {
373                         reg = <1>;
374                         remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>;
375                 };
376         };
377 };
378
379 &mux {
380         mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */
381                         <0x34 0x00000038>, /* IPU_CSI1_MUX */
382                         <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
383                         <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
384                         <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
385                         <0x28 0x00000003>, /* DCIC1_MUX_CTL */
386                         <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
387 };
388
389 &vpu {
390         compatible = "fsl,imx6dl-vpu", "cnm,coda960";
391 };