arch/arm/dts/imx6dl-mamoj.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (C) 2018 BTicino
   4  * Copyright (C) 2018 Amarula Solutions B.V.
   5  */
   6
   7 /dts-v1/;
   8
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include "imx6dl.dtsi"
  11
  12 / {
  13         model = "BTicino i.MX6DL Mamoj board";
  14         compatible = "bticino,imx6dl-mamoj", "fsl,imx6dl";
  15 };
  16
  17 &fec {
  18         pinctrl-names = "default";
  19         pinctrl-0 = <&pinctrl_enet>;
  20         phy-mode = "mii";
  21         status = "okay";
  22 };
  23
  24 &i2c3 {
  25         clock-frequency = <400000>;
  26         pinctrl-names = "default";
  27         pinctrl-0 = <&pinctrl_i2c3>;
  28         status = "okay";
  29 };
  30
  31 &i2c4 {
  32         clock-frequency = <100000>;
  33         pinctrl-names = "default";
  34         pinctrl-0 = <&pinctrl_i2c4>;
  35         status = "okay";
  36
  37         pmic: pfuze100@08 {
  38                 compatible = "fsl,pfuze100";
  39                 reg = <0x08>;
  40
  41                 regulators {
  42                         /* CPU vdd_arm core */
  43                         sw1a_reg: sw1ab {
  44                                 regulator-min-microvolt = <300000>;
  45                                 regulator-max-microvolt = <1875000>;
  46                                 regulator-boot-on;
  47                                 regulator-always-on;
  48                                 regulator-ramp-delay = <6250>;
  49                         };
  50
  51                         /* SOC vdd_soc */
  52                         sw1c_reg: sw1c {
  53                                 regulator-min-microvolt = <300000>;
  54                                 regulator-max-microvolt = <1875000>;
  55                                 regulator-boot-on;
  56                                 regulator-always-on;
  57                                 regulator-ramp-delay = <6250>;
  58                         };
  59
  60                         /* I/O power GEN_3V3 */
  61                         sw2_reg: sw2 {
  62                                 regulator-min-microvolt = <800000>;
  63                                 regulator-max-microvolt = <3300000>;
  64                                 regulator-boot-on;
  65                                 regulator-always-on;
  66                         };
  67
  68                         /* DDR memory */
  69                         sw3a_reg: sw3a {
  70                                 regulator-min-microvolt = <400000>;
  71                                 regulator-max-microvolt = <1975000>;
  72                                 regulator-boot-on;
  73                                 regulator-always-on;
  74                         };
  75
  76                         /* DDR memory */
  77                         sw3b_reg: sw3b {
  78                                 regulator-min-microvolt = <400000>;
  79                                 regulator-max-microvolt = <1975000>;
  80                                 regulator-boot-on;
  81                                 regulator-always-on;
  82                         };
  83
  84                         /* not used */
  85                         sw4_reg: sw4 {
  86                                 regulator-min-microvolt = <800000>;
  87                                 regulator-max-microvolt = <3300000>;
  88                         };
  89
  90                         /* not used */
  91                         swbst_reg: swbst {
  92                                 regulator-min-microvolt = <5000000>;
  93                                 regulator-max-microvolt = <5150000>;
  94                         };
  95
  96                         /* PMIC vsnvs. EX boot mode */
  97                         snvs_reg: vsnvs {
  98                                 regulator-min-microvolt = <1000000>;
  99                                 regulator-max-microvolt = <3000000>;
 100                                 regulator-boot-on;
 101                                 regulator-always-on;
 102                         };
 103
 104                         vref_reg: vrefddr {
 105                                 regulator-boot-on;
 106                                 regulator-always-on;
 107                         };
 108
 109                         /* not used */
 110                         vgen1_reg: vgen1 {
 111                                 regulator-min-microvolt = <800000>;
 112                                 regulator-max-microvolt = <1550000>;
 113                         };
 114
 115                         /* not used */
 116                         vgen2_reg: vgen2 {
 117                                 regulator-min-microvolt = <800000>;
 118                                 regulator-max-microvolt = <1550000>;
 119                         };
 120
 121                         /* not used */
 122                         vgen3_reg: vgen3 {
 123                                 regulator-min-microvolt = <1800000>;
 124                                 regulator-max-microvolt = <3300000>;
 125                         };
 126
 127                         /* 1v8 general power */
 128                         vgen4_reg: vgen4 {
 129                                 regulator-min-microvolt = <1800000>;
 130                                 regulator-max-microvolt = <3300000>;
 131                                 regulator-always-on;
 132                         };
 133
 134                         /* 2v8 general power IMX6 */
 135                         vgen5_reg: vgen5 {
 136                                 regulator-min-microvolt = <1800000>;
 137                                 regulator-max-microvolt = <3300000>;
 138                                 regulator-always-on;
 139                         };
 140
 141                         /* 3v3 Ethernet */
 142                         vgen6_reg: vgen6 {
 143                                 regulator-min-microvolt = <1800000>;
 144                                 regulator-max-microvolt = <3300000>;
 145                                 regulator-always-on;
 146                         };
 147                 };
 148         };
 149 };
 150
 151 &uart3 {
 152         pinctrl-names = "default";
 153         pinctrl-0 = <&pinctrl_uart3>;
 154         status = "okay";
 155 };
 156
 157 &usdhc3 {
 158         pinctrl-names = "default";
 159         pinctrl-0 = <&pinctrl_usdhc3>;
 160         bus-width = <8>;
 161         non-removable;
 162         keep-power-in-suspend;
 163         status = "okay";
 164 };
 165
 166 &iomuxc {
 167         pinctrl_enet: enetgrp {
 168                 fsl,pins = <
 169                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 170                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 171                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b1
 172                         MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x1b0b0
 173                         MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x1b0b0
 174                         MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2      0x1b0b0
 175                         MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3      0x1b0b0
 176                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
 177                         MX6QDL_PAD_GPIO_19__ENET_TX_ER          0x1b0b0
 178                         MX6QDL_PAD_GPIO_18__ENET_RX_CLK         0x1b0b1
 179                         MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x1b0b0
 180                         MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x1b0b0
 181                         MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2      0x1b0b0
 182                         MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3      0x1b0b0
 183                         MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x1b0b0
 184                         MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x1b0b0
 185                         MX6QDL_PAD_KEY_COL3__ENET_CRS           0x1b0b0
 186                         MX6QDL_PAD_KEY_ROW1__ENET_COL           0x1b0b0
 187                 >;
 188         };
 189
 190         pinctrl_i2c3: i2c3grp {
 191                 fsl,pins = <
 192                         MX6QDL_PAD_GPIO_3__I2C3_SCL     0x4001b8b1
 193                         MX6QDL_PAD_GPIO_6__I2C3_SDA     0x4001b8b1
 194                 >;
 195         };
 196
 197         pinctrl_i2c4: i2c4grp {
 198                 fsl,pins = <
 199                         MX6QDL_PAD_GPIO_7__I2C4_SCL     0x4001b8b1
 200                         MX6QDL_PAD_GPIO_8__I2C4_SDA     0x4001b8b1
 201                 >;
 202         };
 203
 204         pinctrl_uart3: uart3grp {
 205                 fsl,pins = <
 206                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 207                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 208                 >;
 209         };
 210
 211         pinctrl_usdhc3: usdhc3grp {
 212                 fsl,pins = <
 213                         MX6QDL_PAD_SD3_CMD__SD3_CMD     0x17059
 214                         MX6QDL_PAD_SD3_CLK__SD3_CLK     0x10059
 215                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0  0x17059
 216                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1  0x17059
 217                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2  0x17059
 218                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3  0x17059
 219                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4  0x17059
 220                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5  0x17059
 221                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6  0x17059
 222                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7  0x17059
 223                 >;
 224         };
 225 };