arch/arm/dts/imx6dl-aristainetos2_4.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0)
   2 /*
   3  * support for the imx6 based aristainetos2 board
   4  * parts for 4.3 inch LG display on the parallel port and atmel maxtouch
   5  *
   6  * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
   7  * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
   8  *
   9  */
  10 /dts-v1/;
  11 #include "imx6dl.dtsi"
  12
  13 / {
  14         display0: disp0 {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17                 compatible = "fsl,imx-parallel-display";
  18                 interface-pix-fmt = "rgb24";
  19                 pinctrl-names = "default";
  20                 pinctrl-0 = <&pinctrl_ipu_disp>;
  21
  22                 port@0 {
  23                         reg = <0>;
  24                         display0_in: endpoint {
  25                                 remote-endpoint = <&ipu1_di0_disp0>;
  26                         };
  27                 };
  28
  29                 port@1 {
  30                         reg = <1>;
  31                         display_out: endpoint {
  32                                 remote-endpoint = <&panel_in>;
  33                         };
  34                 };
  35         };
  36 };
  37
  38 &i2c3 {
  39         touch: touch@4b {
  40                 compatible = "atmel,maxtouch";
  41                 reg = <0x4b>;
  42                 interrupt-parent = <&gpio2>;
  43                 interrupts = <9 8>;
  44         };
  45 };
  46
  47 &ipu1_di0_disp0 {
  48         remote-endpoint = <&display0_in>;
  49 };
  50
  51 &iomuxc {
  52         pinctrl_ipu_disp: ipudisp1grp {
  53                 fsl,pins = <
  54                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x31
  55                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0xE1
  56                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
  57                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
  58                         MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0xE1
  59                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0xE1
  60                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0xE1
  61                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0xE1
  62                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0xE1
  63                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0xE1
  64                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0xE1
  65                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0xE1
  66                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0xE1
  67                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0xE1
  68                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0xE1
  69                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0xE1
  70                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0xE1
  71                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0xE1
  72                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0xe1
  73                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0xE1
  74                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0xE1
  75                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0xE1
  76                         MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0xE1
  77                         MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0xE1
  78                         MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0xE1
  79                         MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0xE1
  80                         MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0xE1
  81                         MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0xE1
  82                 >;
  83         };
  84 };