2 * dts file for Hisilicon Hi6220 SoC
4 * Copyright (C) 2015, Hisilicon Ltd.
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/hi6220-clock.h>
11 compatible = "hisilicon,hi6220";
12 interrupt-parent = <&gic>;
17 compatible = "arm,psci-0.2";
57 compatible = "arm,cortex-a53", "arm,armv8";
60 enable-method = "psci";
64 compatible = "arm,cortex-a53", "arm,armv8";
67 enable-method = "psci";
71 compatible = "arm,cortex-a53", "arm,armv8";
74 enable-method = "psci";
78 compatible = "arm,cortex-a53", "arm,armv8";
81 enable-method = "psci";
85 compatible = "arm,cortex-a53", "arm,armv8";
88 enable-method = "psci";
92 compatible = "arm,cortex-a53", "arm,armv8";
95 enable-method = "psci";
99 compatible = "arm,cortex-a53", "arm,armv8";
102 enable-method = "psci";
106 compatible = "arm,cortex-a53", "arm,armv8";
109 enable-method = "psci";
113 gic: interrupt-controller@f6801000 {
114 compatible = "arm,gic-400";
115 reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
116 <0x0 0xf6802000 0 0x2000>, /* GICC */
117 <0x0 0xf6804000 0 0x2000>, /* GICH */
118 <0x0 0xf6806000 0 0x2000>; /* GICV */
119 #address-cells = <0>;
120 #interrupt-cells = <3>;
121 interrupt-controller;
122 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
126 compatible = "arm,armv8-timer";
127 interrupt-parent = <&gic>;
128 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
129 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
130 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
131 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
135 compatible = "simple-bus";
136 #address-cells = <2>;
140 ao_ctrl: ao_ctrl@f7800000 {
141 compatible = "hisilicon,hi6220-aoctrl", "syscon";
142 reg = <0x0 0xf7800000 0x0 0x2000>;
146 sys_ctrl: sys_ctrl@f7030000 {
147 compatible = "hisilicon,hi6220-sysctrl", "syscon";
148 reg = <0x0 0xf7030000 0x0 0x2000>;
153 media_ctrl: media_ctrl@f4410000 {
154 compatible = "hisilicon,hi6220-mediactrl", "syscon";
155 reg = <0x0 0xf4410000 0x0 0x1000>;
159 pm_ctrl: pm_ctrl@f7032000 {
160 compatible = "hisilicon,hi6220-pmctrl", "syscon";
161 reg = <0x0 0xf7032000 0x0 0x1000>;
165 mmc0: dwmmc@f723d000 {
166 compatible = "hisilicon,hi6220-dw-mshc";
167 reg = <0x0 0xf723d000 0x0 0x1000>;
168 interrupts = <0x0 0x48 0x4>;
169 clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
170 clock-names = "ciu", "biu";
174 mmc1: dwmmc@f723e000 {
175 compatible = "hisilicon,hi6220-dw-mshc";
176 reg = <0x0 0xf723e000 0x0 0x1000>;
177 interrupts = <0x0 0x49 0x4>;
178 clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
179 clock-names = "ciu", "biu";
183 uart0: uart@f8015000 { /* console */
184 compatible = "arm,pl011", "arm,primecell";
185 reg = <0x0 0xf8015000 0x0 0x1000>;
186 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&ao_ctrl HI6220_UART0_PCLK>,
189 <&ao_ctrl HI6220_UART0_PCLK>;
190 clock-names = "uartclk", "apb_pclk";
193 uart1: uart@f7111000 {
194 compatible = "arm,pl011", "arm,primecell";
195 reg = <0x0 0xf7111000 0x0 0x1000>;
196 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
198 clocks = <&sys_ctrl HI6220_UART1_PCLK>,
199 <&sys_ctrl HI6220_UART1_PCLK>;
200 clock-names = "uartclk", "apb_pclk";
204 uart2: uart@f7112000 {
205 compatible = "arm,pl011", "arm,primecell";
206 reg = <0x0 0xf7112000 0x0 0x1000>;
207 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&sys_ctrl HI6220_UART2_PCLK>,
210 <&sys_ctrl HI6220_UART2_PCLK>;
211 clock-names = "uartclk", "apb_pclk";
215 uart3: uart@f7113000 {
216 compatible = "arm,pl011", "arm,primecell";
217 reg = <0x0 0xf7113000 0x0 0x1000>;
218 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&sys_ctrl HI6220_UART3_PCLK>,
221 <&sys_ctrl HI6220_UART3_PCLK>;
222 clock-names = "uartclk", "apb_pclk";
225 uart4: uart@f7114000 {
226 compatible = "arm,pl011", "arm,primecell";
227 reg = <0x0 0xf7114000 0x0 0x1000>;
228 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&sys_ctrl HI6220_UART4_PCLK>,
231 <&sys_ctrl HI6220_UART4_PCLK>;
232 clock-names = "uartclk", "apb_pclk";