arch/arm/dts/fsl-lx2160a.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * NXP lx2160a SOC common device tree source
   4  *
   5  * Copyright 2018 NXP
   6  *
   7  */
   8
   9 / {
  10         compatible = "fsl,lx2160a";
  11         interrupt-parent = <&gic>;
  12         #address-cells = <2>;
  13         #size-cells = <2>;
  14
  15         memory@80000000 {
  16                 device_type = "memory";
  17                 reg = <0x00000000 0x80000000 0 0x80000000>;
  18                       /* DRAM space - 1, size : 2 GB DRAM */
  19         };
  20
  21         sysclk: sysclk {
  22                 compatible = "fixed-clock";
  23                 #clock-cells = <0>;
  24                 clock-frequency = <100000000>;
  25                 clock-output-names = "sysclk";
  26         };
  27
  28         clockgen: clocking@1300000 {
  29                 compatible = "fsl,ls2080a-clockgen";
  30                 reg = <0 0x1300000 0 0xa0000>;
  31                 #clock-cells = <2>;
  32                 clocks = <&sysclk>;
  33         };
  34
  35         gic: interrupt-controller@6000000 {
  36                 compatible = "arm,gic-v3";
  37                 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
  38                       <0x0 0x06200000 0 0x100000>; /* GICR */
  39                 #interrupt-cells = <3>;
  40                 interrupt-controller;
  41                 interrupts = <1 9 0x4>;
  42         };
  43
  44         timer {
  45                 compatible = "arm,armv8-timer";
  46                 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
  47                              <1 14 0x8>, /* Physical NS PPI, active-low */
  48                              <1 11 0x8>, /* Virtual PPI, active-low */
  49                              <1 10 0x8>; /* Hypervisor PPI, active-low */
  50         };
  51
  52         i2c0: i2c@2000000 {
  53                 compatible = "fsl,vf610-i2c";
  54                 #address-cells = <1>;
  55                 #size-cells = <0>;
  56                 reg = <0x0 0x2000000 0x0 0x10000>;
  57                 interrupts = <0 34 4>;
  58                 scl-gpio = <&gpio2 15 0>;
  59                 status = "disabled";
  60         };
  61
  62         i2c1: i2c@2010000 {
  63                 compatible = "fsl,vf610-i2c";
  64                 #address-cells = <1>;
  65                 #size-cells = <0>;
  66                 reg = <0x0 0x2010000 0x0 0x10000>;
  67                 interrupts = <0 34 4>;
  68                 status = "disabled";
  69         };
  70
  71         i2c2: i2c@2020000 {
  72                 compatible = "fsl,vf610-i2c";
  73                 #address-cells = <1>;
  74                 #size-cells = <0>;
  75                 reg = <0x0 0x2020000 0x0 0x10000>;
  76                 interrupts = <0 35 4>;
  77                 status = "disabled";
  78         };
  79
  80         i2c3: i2c@2030000 {
  81                 compatible = "fsl,vf610-i2c";
  82                 #address-cells = <1>;
  83                 #size-cells = <0>;
  84                 reg = <0x0 0x2030000 0x0 0x10000>;
  85                 interrupts = <0 35 4>;
  86                 status = "disabled";
  87         };
  88
  89         i2c4: i2c@2040000 {
  90                 compatible = "fsl,vf610-i2c";
  91                 #address-cells = <1>;
  92                 #size-cells = <0>;
  93                 reg = <0x0 0x2040000 0x0 0x10000>;
  94                 interrupts = <0 74 4>;
  95                 scl-gpio = <&gpio2 16 0>;
  96                 status = "disabled";
  97         };
  98
  99         i2c5: i2c@2050000 {
 100                 compatible = "fsl,vf610-i2c";
 101                 #address-cells = <1>;
 102                 #size-cells = <0>;
 103                 reg = <0x0 0x2050000 0x0 0x10000>;
 104                 interrupts = <0 74 4>;
 105                 status = "disabled";
 106         };
 107
 108         i2c6: i2c@2060000 {
 109                 compatible = "fsl,vf610-i2c";
 110                 #address-cells = <1>;
 111                 #size-cells = <0>;
 112                 reg = <0x0 0x2060000 0x0 0x10000>;
 113                 interrupts = <0 75 4>;
 114                 status = "disabled";
 115         };
 116
 117         i2c7: i2c@2070000 {
 118                 compatible = "fsl,vf610-i2c";
 119                 #address-cells = <1>;
 120                 #size-cells = <0>;
 121                 reg = <0x0 0x2070000 0x0 0x10000>;
 122                 interrupts = <0 75 4>;
 123                 status = "disabled";
 124         };
 125
 126         uart0: serial@21c0000 {
 127                 compatible = "arm,pl011";
 128                 reg = <0x0 0x21c0000 0x0 0x1000>;
 129                 clocks = <&clockgen 4 0>;
 130                 status = "disabled";
 131         };
 132
 133         uart1: serial@21d0000 {
 134                 compatible = "arm,pl011";
 135                 reg = <0x0 0x21d0000 0x0 0x1000>;
 136                 clocks = <&clockgen 4 0>;
 137                 status = "disabled";
 138         };
 139
 140         uart2: serial@21e0000 {
 141                 compatible = "arm,pl011";
 142                 reg = <0x0 0x21e0000 0x0 0x1000>;
 143                 clocks = <&clockgen 4 0>;
 144                 status = "disabled";
 145         };
 146
 147         uart3: serial@21f0000 {
 148                 compatible = "arm,pl011";
 149                 reg = <0x0 0x21f0000 0x0 0x1000>;
 150                 clocks = <&clockgen 4 0>;
 151                 status = "disabled";
 152         };
 153
 154         dspi0: dspi@2100000 {
 155                 compatible = "fsl,vf610-dspi";
 156                 #address-cells = <1>;
 157                 #size-cells = <0>;
 158                 reg = <0x0 0x2100000 0x0 0x10000>;
 159                 interrupts = <0 26 0x4>; /* Level high type */
 160                 num-cs = <6>;
 161         };
 162
 163         dspi1: dspi@2110000 {
 164                 compatible = "fsl,vf610-dspi";
 165                 #address-cells = <1>;
 166                 #size-cells = <0>;
 167                 reg = <0x0 0x2110000 0x0 0x10000>;
 168                 interrupts = <0 26 0x4>; /* Level high type */
 169                 num-cs = <6>;
 170         };
 171
 172         dspi2: dspi@2120000 {
 173                 compatible = "fsl,vf610-dspi";
 174                 #address-cells = <1>;
 175                 #size-cells = <0>;
 176                 reg = <0x0 0x2120000 0x0 0x10000>;
 177                 interrupts = <0 241 0x4>; /* Level high type */
 178                 num-cs = <6>;
 179         };
 180
 181         gpio2: gpio@2320000 {
 182                 compatible = "fsl,qoriq-gpio";
 183                 reg = <0x0 0x2320000 0x0 0x10000>;
 184                 interrupts = <0 37 4>;
 185                 gpio-controller;
 186                 little-endian;
 187                 #gpio-cells = <2>;
 188                 interrupt-controller;
 189                 #interrupt-cells = <2>;
 190         };
 191
 192         usb0: usb3@3100000 {
 193                 compatible = "fsl,layerscape-dwc3";
 194                 reg = <0x0 0x3100000 0x0 0x10000>;
 195                 interrupts = <0 80 0x4>; /* Level high type */
 196                 dr_mode = "host";
 197         };
 198
 199         usb1: usb3@3110000 {
 200                 compatible = "fsl,layerscape-dwc3";
 201                 reg = <0x0 0x3110000 0x0 0x10000>;
 202                 interrupts = <0 81 0x4>; /* Level high type */
 203                 dr_mode = "host";
 204         };
 205
 206         esdhc0: esdhc@2140000 {
 207                 compatible = "fsl,esdhc";
 208                 reg = <0x0 0x2140000 0x0 0x10000>;
 209                 interrupts = <0 28 0x4>; /* Level high type */
 210                 clocks = <&clockgen 4 1>;
 211                 voltage-ranges = <1800 1800 3300 3300>;
 212                 sdhci,auto-cmd12;
 213                 little-endian;
 214                 bus-width = <4>;
 215                 status = "disabled";
 216         };
 217
 218         esdhc1: esdhc@2150000 {
 219                 compatible = "fsl,esdhc";
 220                 reg = <0x0 0x2150000 0x0 0x10000>;
 221                 interrupts = <0 63 0x4>; /* Level high type */
 222                 clocks = <&clockgen 4 1>;
 223                 voltage-ranges = <1800 1800 3300 3300>;
 224                 sdhci,auto-cmd12;
 225                 non-removable;
 226                 little-endian;
 227                 bus-width = <4>;
 228                 status = "disabled";
 229         };
 230
 231         sata0: sata@3200000 {
 232                         compatible = "fsl,ls2080a-ahci";
 233                         reg = <0x0 0x3200000 0x0 0x10000>;
 234                         interrupts = <0 133 4>;
 235                         clocks = <&clockgen 4 3>;
 236                         status = "disabled";
 237
 238         };
 239
 240         sata1: sata@3210000 {
 241                         compatible = "fsl,ls2080a-ahci";
 242                         reg = <0x0 0x3210000 0x0 0x10000>;
 243                         interrupts = <0 136 4>;
 244                         clocks = <&clockgen 4 3>;
 245                         status = "disabled";
 246
 247         };
 248
 249         sata2: sata@3220000 {
 250                         compatible = "fsl,ls2080a-ahci";
 251                         reg = <0x0 0x3220000 0x0 0x10000>;
 252                         interrupts = <0 97 4>;
 253                         clocks = <&clockgen 4 3>;
 254                         status = "disabled";
 255
 256         };
 257
 258         sata3: sata@3230000 {
 259                         compatible = "fsl,ls2080a-ahci";
 260                         reg = <0x0 0x3230000 0x0 0x10000>;
 261                         interrupts = <0 100 4>;
 262                         clocks = <&clockgen 4 3>;
 263                         status = "disabled";
 264
 265         };
 266
 267         pcie@3400000 {
 268                 compatible = "fsl,lx2160a-pcie";
 269                 reg = <0x00 0x03400000 0x0 0x80000   /* PAB registers */
 270                        0x00 0x03480000 0x0 0x40000   /* LUT registers */
 271                        0x00 0x034c0000 0x0 0x40000   /* PF control registers */
 272                        0x80 0x00000000 0x0 0x1000>; /* configuration space */
 273                 reg-names = "ccsr", "lut", "pf_ctrl", "config";
 274                 #address-cells = <3>;
 275                 #size-cells = <2>;
 276                 device_type = "pci";
 277                 bus-range = <0x0 0xff>;
 278                 ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
 279         };
 280
 281         pcie@3500000 {
 282                 compatible = "fsl,lx2160a-pcie";
 283                 reg = <0x00 0x03500000 0x0 0x80000   /* PAB registers */
 284                        0x00 0x03580000 0x0 0x40000   /* LUT registers */
 285                        0x00 0x035c0000 0x0 0x40000   /* PF control registers */
 286                        0x88 0x00000000 0x0 0x1000>; /* configuration space */
 287                 reg-names = "ccsr", "lut", "pf_ctrl", "config";
 288                 #address-cells = <3>;
 289                 #size-cells = <2>;
 290                 device_type = "pci";
 291                 num-lanes = <2>;
 292                 bus-range = <0x0 0xff>;
 293                 ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>;
 294         };
 295
 296         pcie@3600000 {
 297                 compatible = "fsl,lx2160a-pcie";
 298                 reg = <0x00 0x03600000 0x0 0x80000   /* PAB registers */
 299                        0x00 0x03680000 0x0 0x40000   /* LUT registers */
 300                        0x00 0x036c0000 0x0 0x40000   /* PF control registers */
 301                        0x90 0x00000000 0x0 0x1000>; /* configuration space */
 302                 reg-names = "ccsr", "lut", "pf_ctrl", "config";
 303                 #address-cells = <3>;
 304                 #size-cells = <2>;
 305                 device_type = "pci";
 306                 bus-range = <0x0 0xff>;
 307                 ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>;
 308         };
 309
 310         pcie@3700000 {
 311                 compatible = "fsl,lx2160a-pcie";
 312                 reg = <0x00 0x03700000 0x0 0x80000   /* PAB registers */
 313                        0x00 0x03780000 0x0 0x40000   /* LUT registers */
 314                        0x00 0x037c0000 0x0 0x40000   /* PF control registers */
 315                        0x98 0x00000000 0x0 0x1000>; /* configuration space */
 316                 reg-names = "ccsr", "lut", "pf_ctrl", "config";
 317                 #address-cells = <3>;
 318                 #size-cells = <2>;
 319                 device_type = "pci";
 320                 bus-range = <0x0 0xff>;
 321                 ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>;
 322         };
 323
 324         pcie@3800000 {
 325                 compatible = "fsl,lx2160a-pcie";
 326                 reg = <0x00 0x03800000 0x0 0x80000   /* PAB registers */
 327                        0x00 0x03880000 0x0 0x40000   /* LUT registers */
 328                        0x00 0x038c0000 0x0 0x40000   /* PF control registers */
 329                        0xa0 0x00000000 0x0 0x1000>; /* configuration space */
 330                 reg-names = "ccsr", "lut", "pf_ctrl", "config";
 331                 #address-cells = <3>;
 332                 #size-cells = <2>;
 333                 device_type = "pci";
 334                 bus-range = <0x0 0xff>;
 335                 ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>;
 336         };
 337
 338         pcie@3900000 {
 339                 compatible = "fsl,lx2160a-pcie";
 340                 reg = <0x00 0x03900000 0x0 0x80000   /* PAB registers */
 341                        0x00 0x03980000 0x0 0x40000   /* LUT registers */
 342                        0x00 0x039c0000 0x0 0x40000   /* PF control registers */
 343                        0xa8 0x00000000 0x0 0x1000>; /* configuration space */
 344                 reg-names = "ccsr", "lut", "pf_ctrl", "config";
 345                 #address-cells = <3>;
 346                 #size-cells = <2>;
 347                 device_type = "pci";
 348                 bus-range = <0x0 0xff>;
 349                 ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>;
 350         };
 351 };