1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * NXP lx2160a SOC common device tree source
5 * Copyright 2018-2020 NXP
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "fsl,lx2160a";
13 interrupt-parent = <&gic>;
18 device_type = "memory";
19 reg = <0x00000000 0x80000000 0 0x80000000>;
20 /* DRAM space - 1, size : 2 GB DRAM */
24 compatible = "fixed-clock";
26 clock-frequency = <100000000>;
27 clock-output-names = "sysclk";
30 clockgen: clocking@1300000 {
31 compatible = "fsl,ls2080a-clockgen";
32 reg = <0 0x1300000 0 0xa0000>;
37 gic: interrupt-controller@6000000 {
38 compatible = "arm,gic-v3";
39 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
40 <0x0 0x06200000 0 0x100000>; /* GICR */
41 #interrupt-cells = <3>;
43 interrupts = <1 9 0x4>;
46 gic_lpi_base: syscon@0x80000000 {
47 compatible = "gic-lpi-base";
48 reg = <0x0 0x80000000 0x0 0x200000>;
49 max-gic-redistributors = <16>;
53 compatible = "arm,armv8-timer";
54 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
55 <1 14 0x8>, /* Physical NS PPI, active-low */
56 <1 11 0x8>, /* Virtual PPI, active-low */
57 <1 10 0x8>; /* Hypervisor PPI, active-low */
60 fspi: flexspi@20c0000 {
61 compatible = "nxp,lx2160a-fspi";
64 reg = <0x0 0x20c0000 0x0 0x10000>,
65 <0x0 0x20000000 0x0 0x10000000>;
66 reg-names = "fspi_base", "fspi_mmap";
67 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
68 clock-names = "fspi_en", "fspi";
69 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
74 compatible = "fsl,vf610-i2c";
77 reg = <0x0 0x2000000 0x0 0x10000>;
78 interrupts = <0 34 4>;
79 scl-gpio = <&gpio2 15 0>;
84 compatible = "fsl,vf610-i2c";
87 reg = <0x0 0x2010000 0x0 0x10000>;
88 interrupts = <0 34 4>;
93 compatible = "fsl,vf610-i2c";
96 reg = <0x0 0x2020000 0x0 0x10000>;
97 interrupts = <0 35 4>;
102 compatible = "fsl,vf610-i2c";
103 #address-cells = <1>;
105 reg = <0x0 0x2030000 0x0 0x10000>;
106 interrupts = <0 35 4>;
111 compatible = "fsl,vf610-i2c";
112 #address-cells = <1>;
114 reg = <0x0 0x2040000 0x0 0x10000>;
115 interrupts = <0 74 4>;
116 scl-gpio = <&gpio2 16 0>;
121 compatible = "fsl,vf610-i2c";
122 #address-cells = <1>;
124 reg = <0x0 0x2050000 0x0 0x10000>;
125 interrupts = <0 74 4>;
130 compatible = "fsl,vf610-i2c";
131 #address-cells = <1>;
133 reg = <0x0 0x2060000 0x0 0x10000>;
134 interrupts = <0 75 4>;
139 compatible = "fsl,vf610-i2c";
140 #address-cells = <1>;
142 reg = <0x0 0x2070000 0x0 0x10000>;
143 interrupts = <0 75 4>;
147 uart0: serial@21c0000 {
148 compatible = "arm,pl011";
149 reg = <0x0 0x21c0000 0x0 0x1000>;
150 clocks = <&clockgen 4 0>;
154 uart1: serial@21d0000 {
155 compatible = "arm,pl011";
156 reg = <0x0 0x21d0000 0x0 0x1000>;
157 clocks = <&clockgen 4 0>;
161 uart2: serial@21e0000 {
162 compatible = "arm,pl011";
163 reg = <0x0 0x21e0000 0x0 0x1000>;
164 clocks = <&clockgen 4 0>;
168 uart3: serial@21f0000 {
169 compatible = "arm,pl011";
170 reg = <0x0 0x21f0000 0x0 0x1000>;
171 clocks = <&clockgen 4 0>;
175 dspi0: dspi@2100000 {
176 compatible = "fsl,vf610-dspi";
177 #address-cells = <1>;
179 reg = <0x0 0x2100000 0x0 0x10000>;
180 interrupts = <0 26 0x4>; /* Level high type */
184 dspi1: dspi@2110000 {
185 compatible = "fsl,vf610-dspi";
186 #address-cells = <1>;
188 reg = <0x0 0x2110000 0x0 0x10000>;
189 interrupts = <0 26 0x4>; /* Level high type */
193 dspi2: dspi@2120000 {
194 compatible = "fsl,vf610-dspi";
195 #address-cells = <1>;
197 reg = <0x0 0x2120000 0x0 0x10000>;
198 interrupts = <0 241 0x4>; /* Level high type */
202 gpio0: gpio@2300000 {
203 compatible = "fsl,qoriq-gpio";
204 reg = <0x0 0x2300000 0x0 0x10000>;
205 interrupts = <0 36 4>;
209 interrupt-controller;
210 #interrupt-cells = <2>;
213 gpio1: gpio@2310000 {
214 compatible = "fsl,qoriq-gpio";
215 reg = <0x0 0x2310000 0x0 0x10000>;
216 interrupts = <0 36 4>;
220 interrupt-controller;
221 #interrupt-cells = <2>;
224 gpio2: gpio@2320000 {
225 compatible = "fsl,qoriq-gpio";
226 reg = <0x0 0x2320000 0x0 0x10000>;
227 interrupts = <0 37 4>;
231 interrupt-controller;
232 #interrupt-cells = <2>;
235 gpio3: gpio@2330000 {
236 compatible = "fsl,qoriq-gpio";
237 reg = <0x0 0x2330000 0x0 0x10000>;
238 interrupts = <0 37 4>;
242 interrupt-controller;
243 #interrupt-cells = <2>;
247 compatible = "arm,sbsa-gwdt";
248 reg = <0x0 0x23a0000 0 0x1000>,
249 <0x0 0x2390000 0 0x1000>;
254 compatible = "fsl,layerscape-dwc3";
255 reg = <0x0 0x3100000 0x0 0x10000>;
256 interrupts = <0 80 0x4>; /* Level high type */
261 compatible = "fsl,layerscape-dwc3";
262 reg = <0x0 0x3110000 0x0 0x10000>;
263 interrupts = <0 81 0x4>; /* Level high type */
267 esdhc0: esdhc@2140000 {
268 compatible = "fsl,esdhc";
269 reg = <0x0 0x2140000 0x0 0x10000>;
270 interrupts = <0 28 0x4>; /* Level high type */
271 clocks = <&clockgen 4 1>;
272 voltage-ranges = <1800 1800 3300 3300>;
279 esdhc1: esdhc@2150000 {
280 compatible = "fsl,esdhc";
281 reg = <0x0 0x2150000 0x0 0x10000>;
282 interrupts = <0 63 0x4>; /* Level high type */
283 clocks = <&clockgen 4 1>;
284 voltage-ranges = <1800 1800 3300 3300>;
292 sata0: sata@3200000 {
293 compatible = "fsl,ls2080a-ahci";
294 reg = <0x0 0x3200000 0x0 0x10000>;
295 interrupts = <0 133 4>;
296 clocks = <&clockgen 4 3>;
301 sata1: sata@3210000 {
302 compatible = "fsl,ls2080a-ahci";
303 reg = <0x0 0x3210000 0x0 0x10000>;
304 interrupts = <0 136 4>;
305 clocks = <&clockgen 4 3>;
310 sata2: sata@3220000 {
311 compatible = "fsl,ls2080a-ahci";
312 reg = <0x0 0x3220000 0x0 0x10000>;
313 interrupts = <0 97 4>;
314 clocks = <&clockgen 4 3>;
319 sata3: sata@3230000 {
320 compatible = "fsl,ls2080a-ahci";
321 reg = <0x0 0x3230000 0x0 0x10000>;
322 interrupts = <0 100 4>;
323 clocks = <&clockgen 4 3>;
329 compatible = "fsl,lx2160a-pcie";
330 reg = <0x00 0x03400000 0x0 0x80000 /* PAB registers */
331 0x00 0x03480000 0x0 0x40000 /* LUT registers */
332 0x00 0x034c0000 0x0 0x40000 /* PF control registers */
333 0x80 0x00000000 0x0 0x2000>; /* configuration space */
334 reg-names = "ccsr", "lut", "pf_ctrl", "config";
335 #address-cells = <3>;
338 bus-range = <0x0 0xff>;
339 ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */
340 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
344 compatible = "fsl,lx2160a-pcie";
345 reg = <0x00 0x03500000 0x0 0x80000 /* PAB registers */
346 0x00 0x03580000 0x0 0x40000 /* LUT registers */
347 0x00 0x035c0000 0x0 0x40000 /* PF control registers */
348 0x88 0x00000000 0x0 0x2000>; /* configuration space */
349 reg-names = "ccsr", "lut", "pf_ctrl", "config";
350 #address-cells = <3>;
354 bus-range = <0x0 0xff>;
355 ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */
356 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
360 compatible = "fsl,lx2160a-pcie";
361 reg = <0x00 0x03600000 0x0 0x80000 /* PAB registers */
362 0x00 0x03680000 0x0 0x40000 /* LUT registers */
363 0x00 0x036c0000 0x0 0x40000 /* PF control registers */
364 0x90 0x00000000 0x0 0x2000>; /* configuration space */
365 reg-names = "ccsr", "lut", "pf_ctrl", "config";
366 #address-cells = <3>;
369 bus-range = <0x0 0xff>;
370 ranges = <0x81000000 0x0 0x00000000 0x90 0x00020000 0x0 0x00010000 /* downstream I/O */
371 0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
375 compatible = "fsl,lx2160a-pcie";
376 reg = <0x00 0x03700000 0x0 0x80000 /* PAB registers */
377 0x00 0x03780000 0x0 0x40000 /* LUT registers */
378 0x00 0x037c0000 0x0 0x40000 /* PF control registers */
379 0x98 0x00000000 0x0 0x2000>; /* configuration space */
380 reg-names = "ccsr", "lut", "pf_ctrl", "config";
381 #address-cells = <3>;
384 bus-range = <0x0 0xff>;
385 ranges = <0x81000000 0x0 0x00000000 0x98 0x00020000 0x0 0x00010000 /* downstream I/O */
386 0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
390 compatible = "fsl,lx2160a-pcie";
391 reg = <0x00 0x03800000 0x0 0x80000 /* PAB registers */
392 0x00 0x03880000 0x0 0x40000 /* LUT registers */
393 0x00 0x038c0000 0x0 0x40000 /* PF control registers */
394 0xa0 0x00000000 0x0 0x2000>; /* configuration space */
395 reg-names = "ccsr", "lut", "pf_ctrl", "config";
396 #address-cells = <3>;
399 bus-range = <0x0 0xff>;
400 ranges = <0x81000000 0x0 0x00000000 0xa0 0x00020000 0x0 0x00010000 /* downstream I/O */
401 0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
405 compatible = "fsl,lx2160a-pcie";
406 reg = <0x00 0x03900000 0x0 0x80000 /* PAB registers */
407 0x00 0x03980000 0x0 0x40000 /* LUT registers */
408 0x00 0x039c0000 0x0 0x40000 /* PF control registers */
409 0xa8 0x00000000 0x0 0x2000>; /* configuration space */
410 reg-names = "ccsr", "lut", "pf_ctrl", "config";
411 #address-cells = <3>;
414 bus-range = <0x0 0xff>;
415 ranges = <0x81000000 0x0 0x00000000 0xa8 0x00020000 0x0 0x00010000 /* downstream I/O */
416 0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
419 fsl_mc: fsl-mc@80c000000 {
420 compatible = "fsl,qoriq-mc", "simple-mfd";
421 reg = <0x00000008 0x0c000000 0 0x40>,
422 <0x00000000 0x08340000 0 0x40000>;
423 #address-cells = <3>;
427 * Region type 0x0 - MC portals
428 * Region type 0x1 - QBMAN portals
430 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
431 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
434 compatible = "simple-mfd";
435 #address-cells = <1>;
439 compatible = "fsl,qoriq-mc-dpmac";
445 compatible = "fsl,qoriq-mc-dpmac";
451 compatible = "fsl,qoriq-mc-dpmac";
457 compatible = "fsl,qoriq-mc-dpmac";
463 compatible = "fsl,qoriq-mc-dpmac";
469 compatible = "fsl,qoriq-mc-dpmac";
475 compatible = "fsl,qoriq-mc-dpmac";
481 compatible = "fsl,qoriq-mc-dpmac";
487 compatible = "fsl,qoriq-mc-dpmac";
493 compatible = "fsl,qoriq-mc-dpmac";
499 compatible = "fsl,qoriq-mc-dpmac";
505 compatible = "fsl,qoriq-mc-dpmac";
511 compatible = "fsl,qoriq-mc-dpmac";
517 compatible = "fsl,qoriq-mc-dpmac";
523 compatible = "fsl,qoriq-mc-dpmac";
529 compatible = "fsl,qoriq-mc-dpmac";
535 compatible = "fsl,qoriq-mc-dpmac";
541 compatible = "fsl,qoriq-mc-dpmac";
548 /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
549 emdio1: mdio@8b96000 {
550 compatible = "fsl,ls-mdio";
551 reg = <0x0 0x8b96000 0x0 0x1000>;
552 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
553 #address-cells = <1>;
558 /* WRIOP0: 0x8b8_0000, E-MDIO2: 0x1_7000 */
559 emdio2: mdio@8b97000 {
560 compatible = "fsl,ls-mdio";
561 reg = <0x0 0x8b97000 0x0 0x1000>;
562 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
563 #address-cells = <1>;
569 compatible = "linaro,optee-tz";