arch/arm/dts/fsl-lx2160a.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * NXP lx2160a SOC common device tree source
   4  *
   5  * Copyright 2018-2021, 2023 NXP
   6  *
   7  */
   8
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10
  11 / {
  12         compatible = "fsl,lx2160a";
  13         interrupt-parent = <&gic>;
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         memory@80000000 {
  18                 device_type = "memory";
  19                 reg = <0x00000000 0x80000000 0 0x80000000>;
  20                       /* DRAM space - 1, size : 2 GB DRAM */
  21         };
  22
  23         sysclk: sysclk {
  24                 compatible = "fixed-clock";
  25                 #clock-cells = <0>;
  26                 clock-frequency = <100000000>;
  27                 clock-output-names = "sysclk";
  28         };
  29
  30         soc {
  31                 compatible = "simple-bus";
  32                 #address-cells = <2>;
  33                 #size-cells = <2>;
  34                 ranges;
  35                 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
  36
  37                 uart0: serial@21c0000 {
  38                         compatible = "arm,sbsa-uart","arm,pl011";
  39                         reg = <0x0 0x21c0000 0x0 0x1000>;
  40                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  41                         current-speed = <115200>;
  42                         status = "disabled";
  43                         bootph-all;
  44                 };
  45
  46                 uart1: serial@21d0000 {
  47                         compatible = "arm,sbsa-uart","arm,pl011";
  48                         reg = <0x0 0x21d0000 0x0 0x1000>;
  49                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
  50                         current-speed = <115200>;
  51                         status = "disabled";
  52                         bootph-all;
  53                 };
  54
  55                 uart2: serial@21e0000 {
  56                         compatible = "arm,sbsa-uart","arm,pl011";
  57                         reg = <0x0 0x21e0000 0x0 0x1000>;
  58                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  59                         current-speed = <115200>;
  60                         status = "disabled";
  61                         bootph-all;
  62                 };
  63
  64                 uart3: serial@21f0000 {
  65                         compatible = "arm,sbsa-uart","arm,pl011";
  66                         reg = <0x0 0x21f0000 0x0 0x1000>;
  67                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  68                         current-speed = <115200>;
  69                         status = "disabled";
  70                         bootph-all;
  71                 };
  72         };
  73
  74         crypto: crypto@8000000 {
  75                 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
  76                 fsl,sec-era = <10>;
  77                 #address-cells = <1>;
  78                 #size-cells = <1>;
  79                 ranges = <0x0 0x00 0x8000000 0x100000>;
  80                 reg = <0x00 0x8000000 0x0 0x100000>;
  81                 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
  82                 dma-coherent;
  83
  84                 sec_jr0: jr@10000 {
  85                         compatible = "fsl,sec-v5.0-job-ring",
  86                                      "fsl,sec-v4.0-job-ring";
  87                         reg        = <0x10000 0x10000>;
  88                         interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
  89                 };
  90
  91                 sec_jr1: jr@20000 {
  92                         compatible = "fsl,sec-v5.0-job-ring",
  93                                      "fsl,sec-v4.0-job-ring";
  94                         reg        = <0x20000 0x10000>;
  95                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
  96                 };
  97
  98                 sec_jr2: jr@30000 {
  99                         compatible = "fsl,sec-v5.0-job-ring",
 100                                      "fsl,sec-v4.0-job-ring";
 101                         reg        = <0x30000 0x10000>;
 102                         interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 103                 };
 104
 105                 sec_jr3: jr@40000 {
 106                         compatible = "fsl,sec-v5.0-job-ring",
 107                                      "fsl,sec-v4.0-job-ring";
 108                         reg        = <0x40000 0x10000>;
 109                         interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 110                 };
 111         };
 112
 113         clockgen: clocking@1300000 {
 114                 compatible = "fsl,ls2080a-clockgen";
 115                 reg = <0 0x1300000 0 0xa0000>;
 116                 #clock-cells = <2>;
 117                 clocks = <&sysclk>;
 118         };
 119
 120         gic: interrupt-controller@6000000 {
 121                 compatible = "arm,gic-v3";
 122                 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
 123                       <0x0 0x06200000 0 0x100000>; /* GICR */
 124                 #interrupt-cells = <3>;
 125                 interrupt-controller;
 126                 interrupts = <1 9 0x4>;
 127         };
 128
 129         timer {
 130                 compatible = "arm,armv8-timer";
 131                 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
 132                              <1 14 0x8>, /* Physical NS PPI, active-low */
 133                              <1 11 0x8>, /* Virtual PPI, active-low */
 134                              <1 10 0x8>; /* Hypervisor PPI, active-low */
 135         };
 136
 137         fspi: flexspi@20c0000 {
 138                 compatible = "nxp,lx2160a-fspi";
 139                 #address-cells = <1>;
 140                 #size-cells = <0>;
 141                 reg = <0x0 0x20c0000 0x0 0x10000>,
 142                         <0x0 0x20000000 0x0 0x10000000>;
 143                 reg-names = "fspi_base", "fspi_mmap";
 144                 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 145                 clock-names = "fspi_en", "fspi";
 146                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 147                 status = "disabled";
 148         };
 149
 150         i2c0: i2c@2000000 {
 151                 compatible = "fsl,vf610-i2c";
 152                 #address-cells = <1>;
 153                 #size-cells = <0>;
 154                 reg = <0x0 0x2000000 0x0 0x10000>;
 155                 interrupts = <0 34 4>;
 156                 scl-gpio = <&gpio2 15 0>;
 157                 status = "disabled";
 158         };
 159
 160         i2c1: i2c@2010000 {
 161                 compatible = "fsl,vf610-i2c";
 162                 #address-cells = <1>;
 163                 #size-cells = <0>;
 164                 reg = <0x0 0x2010000 0x0 0x10000>;
 165                 interrupts = <0 34 4>;
 166                 status = "disabled";
 167         };
 168
 169         i2c2: i2c@2020000 {
 170                 compatible = "fsl,vf610-i2c";
 171                 #address-cells = <1>;
 172                 #size-cells = <0>;
 173                 reg = <0x0 0x2020000 0x0 0x10000>;
 174                 interrupts = <0 35 4>;
 175                 status = "disabled";
 176         };
 177
 178         i2c3: i2c@2030000 {
 179                 compatible = "fsl,vf610-i2c";
 180                 #address-cells = <1>;
 181                 #size-cells = <0>;
 182                 reg = <0x0 0x2030000 0x0 0x10000>;
 183                 interrupts = <0 35 4>;
 184                 status = "disabled";
 185         };
 186
 187         i2c4: i2c@2040000 {
 188                 compatible = "fsl,vf610-i2c";
 189                 #address-cells = <1>;
 190                 #size-cells = <0>;
 191                 reg = <0x0 0x2040000 0x0 0x10000>;
 192                 interrupts = <0 74 4>;
 193                 scl-gpio = <&gpio2 16 0>;
 194                 status = "disabled";
 195         };
 196
 197         i2c5: i2c@2050000 {
 198                 compatible = "fsl,vf610-i2c";
 199                 #address-cells = <1>;
 200                 #size-cells = <0>;
 201                 reg = <0x0 0x2050000 0x0 0x10000>;
 202                 interrupts = <0 74 4>;
 203                 status = "disabled";
 204         };
 205
 206         i2c6: i2c@2060000 {
 207                 compatible = "fsl,vf610-i2c";
 208                 #address-cells = <1>;
 209                 #size-cells = <0>;
 210                 reg = <0x0 0x2060000 0x0 0x10000>;
 211                 interrupts = <0 75 4>;
 212                 status = "disabled";
 213         };
 214
 215         i2c7: i2c@2070000 {
 216                 compatible = "fsl,vf610-i2c";
 217                 #address-cells = <1>;
 218                 #size-cells = <0>;
 219                 reg = <0x0 0x2070000 0x0 0x10000>;
 220                 interrupts = <0 75 4>;
 221                 status = "disabled";
 222         };
 223
 224         dspi0: dspi@2100000 {
 225                 compatible = "fsl,vf610-dspi";
 226                 #address-cells = <1>;
 227                 #size-cells = <0>;
 228                 reg = <0x0 0x2100000 0x0 0x10000>;
 229                 interrupts = <0 26 0x4>; /* Level high type */
 230                 spi-num-chipselects = <6>;
 231         };
 232
 233         dspi1: dspi@2110000 {
 234                 compatible = "fsl,vf610-dspi";
 235                 #address-cells = <1>;
 236                 #size-cells = <0>;
 237                 reg = <0x0 0x2110000 0x0 0x10000>;
 238                 interrupts = <0 26 0x4>; /* Level high type */
 239                 spi-num-chipselects = <6>;
 240         };
 241
 242         dspi2: dspi@2120000 {
 243                 compatible = "fsl,vf610-dspi";
 244                 #address-cells = <1>;
 245                 #size-cells = <0>;
 246                 reg = <0x0 0x2120000 0x0 0x10000>;
 247                 interrupts = <0 241 0x4>; /* Level high type */
 248                 spi-num-chipselects = <6>;
 249         };
 250
 251         gpio0: gpio@2300000 {
 252                 compatible = "fsl,qoriq-gpio";
 253                 reg = <0x0 0x2300000 0x0 0x10000>;
 254                 interrupts = <0 36 4>;
 255                 gpio-controller;
 256                 little-endian;
 257                 #gpio-cells = <2>;
 258                 interrupt-controller;
 259                 #interrupt-cells = <2>;
 260         };
 261
 262         gpio1: gpio@2310000 {
 263                 compatible = "fsl,qoriq-gpio";
 264                 reg = <0x0 0x2310000 0x0 0x10000>;
 265                 interrupts = <0 36 4>;
 266                 gpio-controller;
 267                 little-endian;
 268                 #gpio-cells = <2>;
 269                 interrupt-controller;
 270                 #interrupt-cells = <2>;
 271         };
 272
 273         gpio2: gpio@2320000 {
 274                 compatible = "fsl,qoriq-gpio";
 275                 reg = <0x0 0x2320000 0x0 0x10000>;
 276                 interrupts = <0 37 4>;
 277                 gpio-controller;
 278                 little-endian;
 279                 #gpio-cells = <2>;
 280                 interrupt-controller;
 281                 #interrupt-cells = <2>;
 282         };
 283
 284         gpio3: gpio@2330000 {
 285                 compatible = "fsl,qoriq-gpio";
 286                 reg = <0x0 0x2330000 0x0 0x10000>;
 287                 interrupts = <0 37 4>;
 288                 gpio-controller;
 289                 little-endian;
 290                 #gpio-cells = <2>;
 291                 interrupt-controller;
 292                 #interrupt-cells = <2>;
 293         };
 294
 295         watchdog@23a0000 {
 296                 compatible = "arm,sbsa-gwdt";
 297                 reg = <0x0 0x23a0000 0 0x1000>,
 298                       <0x0 0x2390000 0 0x1000>;
 299                 timeout-sec = <30>;
 300         };
 301
 302         usb0: usb3@3100000 {
 303                 compatible = "fsl,layerscape-dwc3";
 304                 reg = <0x0 0x3100000 0x0 0x10000>;
 305                 interrupts = <0 80 0x4>; /* Level high type */
 306                 dr_mode = "host";
 307         };
 308
 309         usb1: usb3@3110000 {
 310                 compatible = "fsl,layerscape-dwc3";
 311                 reg = <0x0 0x3110000 0x0 0x10000>;
 312                 interrupts = <0 81 0x4>; /* Level high type */
 313                 dr_mode = "host";
 314         };
 315
 316         esdhc0: esdhc@2140000 {
 317                 compatible = "fsl,esdhc";
 318                 reg = <0x0 0x2140000 0x0 0x10000>;
 319                 interrupts = <0 28 0x4>; /* Level high type */
 320                 clocks = <&clockgen 4 1>;
 321                 voltage-ranges = <1800 1800 3300 3300>;
 322                 sdhci,auto-cmd12;
 323                 little-endian;
 324                 bus-width = <4>;
 325                 status = "disabled";
 326         };
 327
 328         esdhc1: esdhc@2150000 {
 329                 compatible = "fsl,esdhc";
 330                 reg = <0x0 0x2150000 0x0 0x10000>;
 331                 interrupts = <0 63 0x4>; /* Level high type */
 332                 clocks = <&clockgen 4 1>;
 333                 voltage-ranges = <1800 1800 3300 3300>;
 334                 sdhci,auto-cmd12;
 335                 non-removable;
 336                 little-endian;
 337                 bus-width = <4>;
 338                 status = "disabled";
 339         };
 340
 341         sata0: sata@3200000 {
 342                         compatible = "fsl,ls2080a-ahci";
 343                         reg = <0x0 0x3200000 0x0 0x10000>;
 344                         interrupts = <0 133 4>;
 345                         clocks = <&clockgen 4 3>;
 346                         status = "disabled";
 347
 348         };
 349
 350         sata1: sata@3210000 {
 351                         compatible = "fsl,ls2080a-ahci";
 352                         reg = <0x0 0x3210000 0x0 0x10000>;
 353                         interrupts = <0 136 4>;
 354                         clocks = <&clockgen 4 3>;
 355                         status = "disabled";
 356
 357         };
 358
 359         sata2: sata@3220000 {
 360                         compatible = "fsl,ls2080a-ahci";
 361                         reg = <0x0 0x3220000 0x0 0x10000>;
 362                         interrupts = <0 97 4>;
 363                         clocks = <&clockgen 4 3>;
 364                         status = "disabled";
 365
 366         };
 367
 368         sata3: sata@3230000 {
 369                         compatible = "fsl,ls2080a-ahci";
 370                         reg = <0x0 0x3230000 0x0 0x10000>;
 371                         interrupts = <0 100 4>;
 372                         clocks = <&clockgen 4 3>;
 373                         status = "disabled";
 374
 375         };
 376
 377         pcie1: pcie@3400000 {
 378                 compatible = "fsl,lx2160a-pcie";
 379                 reg = <0x00 0x03400000 0x0 0x80000   /* PAB registers */
 380                        0x00 0x03480000 0x0 0x40000   /* LUT registers */
 381                        0x00 0x034c0000 0x0 0x40000   /* PF control registers */
 382                        0x80 0x00000000 0x0 0x2000>; /* configuration space */
 383                 reg-names = "ccsr", "lut", "pf_ctrl", "config";
 384                 #address-cells = <3>;
 385                 #size-cells = <2>;
 386                 device_type = "pci";
 387                 bus-range = <0x0 0xff>;
 388                 ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000   /* downstream I/O */
 389                           0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 390         };
 391
 392         pcie2: pcie@3500000 {
 393                 compatible = "fsl,lx2160a-pcie";
 394                 reg = <0x00 0x03500000 0x0 0x80000   /* PAB registers */
 395                        0x00 0x03580000 0x0 0x40000   /* LUT registers */
 396                        0x00 0x035c0000 0x0 0x40000   /* PF control registers */
 397                        0x88 0x00000000 0x0 0x2000>; /* configuration space */
 398                 reg-names = "ccsr", "lut", "pf_ctrl", "config";
 399                 #address-cells = <3>;
 400                 #size-cells = <2>;
 401                 device_type = "pci";
 402                 num-lanes = <2>;
 403                 bus-range = <0x0 0xff>;
 404                 ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000   /* downstream I/O */
 405                           0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 406         };
 407
 408         pcie3: pcie@3600000 {
 409                 compatible = "fsl,lx2160a-pcie";
 410                 reg = <0x00 0x03600000 0x0 0x80000   /* PAB registers */
 411                        0x00 0x03680000 0x0 0x40000   /* LUT registers */
 412                        0x00 0x036c0000 0x0 0x40000   /* PF control registers */
 413                        0x90 0x00000000 0x0 0x2000>; /* configuration space */
 414                 reg-names = "ccsr", "lut", "pf_ctrl", "config";
 415                 #address-cells = <3>;
 416                 #size-cells = <2>;
 417                 device_type = "pci";
 418                 bus-range = <0x0 0xff>;
 419                 ranges = <0x81000000 0x0 0x00000000 0x90 0x00020000 0x0 0x00010000   /* downstream I/O */
 420                           0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 421         };
 422
 423         pcie4: pcie@3700000 {
 424                 compatible = "fsl,lx2160a-pcie";
 425                 reg = <0x00 0x03700000 0x0 0x80000   /* PAB registers */
 426                        0x00 0x03780000 0x0 0x40000   /* LUT registers */
 427                        0x00 0x037c0000 0x0 0x40000   /* PF control registers */
 428                        0x98 0x00000000 0x0 0x2000>; /* configuration space */
 429                 reg-names = "ccsr", "lut", "pf_ctrl", "config";
 430                 #address-cells = <3>;
 431                 #size-cells = <2>;
 432                 device_type = "pci";
 433                 bus-range = <0x0 0xff>;
 434                 ranges = <0x81000000 0x0 0x00000000 0x98 0x00020000 0x0 0x00010000   /* downstream I/O */
 435                           0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 436         };
 437
 438         pcie5: pcie@3800000 {
 439                 compatible = "fsl,lx2160a-pcie";
 440                 reg = <0x00 0x03800000 0x0 0x80000   /* PAB registers */
 441                        0x00 0x03880000 0x0 0x40000   /* LUT registers */
 442                        0x00 0x038c0000 0x0 0x40000   /* PF control registers */
 443                        0xa0 0x00000000 0x0 0x2000>; /* configuration space */
 444                 reg-names = "ccsr", "lut", "pf_ctrl", "config";
 445                 #address-cells = <3>;
 446                 #size-cells = <2>;
 447                 device_type = "pci";
 448                 bus-range = <0x0 0xff>;
 449                 ranges = <0x81000000 0x0 0x00000000 0xa0 0x00020000 0x0 0x00010000   /* downstream I/O */
 450                           0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 451         };
 452
 453         pcie6: pcie@3900000 {
 454                 compatible = "fsl,lx2160a-pcie";
 455                 reg = <0x00 0x03900000 0x0 0x80000   /* PAB registers */
 456                        0x00 0x03980000 0x0 0x40000   /* LUT registers */
 457                        0x00 0x039c0000 0x0 0x40000   /* PF control registers */
 458                        0xa8 0x00000000 0x0 0x2000>; /* configuration space */
 459                 reg-names = "ccsr", "lut", "pf_ctrl", "config";
 460                 #address-cells = <3>;
 461                 #size-cells = <2>;
 462                 device_type = "pci";
 463                 bus-range = <0x0 0xff>;
 464                 ranges = <0x81000000 0x0 0x00000000 0xa8 0x00020000 0x0 0x00010000   /* downstream I/O */
 465                           0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 466         };
 467
 468         fsl_mc: fsl-mc@80c000000 {
 469                 compatible = "fsl,qoriq-mc", "simple-mfd";
 470                 reg = <0x00000008 0x0c000000 0 0x40>,
 471                       <0x00000000 0x08340000 0 0x40000>;
 472                 #address-cells = <3>;
 473                 #size-cells = <1>;
 474
 475                 /*
 476                  * Region type 0x0 - MC portals
 477                  * Region type 0x1 - QBMAN portals
 478                  */
 479                 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
 480                           0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
 481
 482                 dpmacs {
 483                         compatible = "simple-mfd";
 484                         #address-cells = <1>;
 485                         #size-cells = <0>;
 486
 487                         dpmac1: dpmac@1 {
 488                                 compatible = "fsl,qoriq-mc-dpmac";
 489                                 reg = <0x1>;
 490                                 status = "disabled";
 491                         };
 492
 493                         dpmac2: dpmac@2 {
 494                                 compatible = "fsl,qoriq-mc-dpmac";
 495                                 reg = <0x2>;
 496                                 status = "disabled";
 497                         };
 498
 499                         dpmac3: dpmac@3 {
 500                                 compatible = "fsl,qoriq-mc-dpmac";
 501                                 reg = <0x3>;
 502                                 status = "disabled";
 503                         };
 504
 505                         dpmac4: dpmac@4 {
 506                                 compatible = "fsl,qoriq-mc-dpmac";
 507                                 reg = <0x4>;
 508                                 status = "disabled";
 509                         };
 510
 511                         dpmac5: dpmac@5 {
 512                                 compatible = "fsl,qoriq-mc-dpmac";
 513                                 reg = <0x5>;
 514                                 status = "disabled";
 515                         };
 516
 517                         dpmac6: dpmac@6 {
 518                                 compatible = "fsl,qoriq-mc-dpmac";
 519                                 reg = <0x6>;
 520                                 status = "disabled";
 521                         };
 522
 523                         dpmac7: dpmac@7 {
 524                                 compatible = "fsl,qoriq-mc-dpmac";
 525                                 reg = <0x7>;
 526                                 status = "disabled";
 527                         };
 528
 529                         dpmac8: dpmac@8 {
 530                                 compatible = "fsl,qoriq-mc-dpmac";
 531                                 reg = <0x8>;
 532                                 status = "disabled";
 533                         };
 534
 535                         dpmac9: dpmac@9 {
 536                                 compatible = "fsl,qoriq-mc-dpmac";
 537                                 reg = <0x9>;
 538                                 status = "disabled";
 539                         };
 540
 541                         dpmac10: dpmac@a {
 542                                 compatible = "fsl,qoriq-mc-dpmac";
 543                                 reg = <0xa>;
 544                                 status = "disabled";
 545                         };
 546
 547                         dpmac11: dpmac@b {
 548                                 compatible = "fsl,qoriq-mc-dpmac";
 549                                 reg = <0xb>;
 550                                 status = "disabled";
 551                         };
 552
 553                         dpmac12: dpmac@c {
 554                                 compatible = "fsl,qoriq-mc-dpmac";
 555                                 reg = <0xc>;
 556                                 status = "disabled";
 557                         };
 558
 559                         dpmac13: dpmac@d {
 560                                 compatible = "fsl,qoriq-mc-dpmac";
 561                                 reg = <0xd>;
 562                                 status = "disabled";
 563                         };
 564
 565                         dpmac14: dpmac@e {
 566                                 compatible = "fsl,qoriq-mc-dpmac";
 567                                 reg = <0xe>;
 568                                 status = "disabled";
 569                         };
 570
 571                         dpmac15: dpmac@f {
 572                                 compatible = "fsl,qoriq-mc-dpmac";
 573                                 reg = <0xf>;
 574                                 status = "disabled";
 575                         };
 576
 577                         dpmac16: dpmac@10 {
 578                                 compatible = "fsl,qoriq-mc-dpmac";
 579                                 reg = <0x10>;
 580                                 status = "disabled";
 581                         };
 582
 583                         dpmac17: dpmac@11 {
 584                                 compatible = "fsl,qoriq-mc-dpmac";
 585                                 reg = <0x11>;
 586                                 status = "disabled";
 587                         };
 588
 589                         dpmac18: dpmac@12 {
 590                                 compatible = "fsl,qoriq-mc-dpmac";
 591                                 reg = <0x12>;
 592                                 status = "disabled";
 593                         };
 594                 };
 595         };
 596
 597         /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
 598         emdio1: mdio@8b96000 {
 599                 compatible = "fsl,ls-mdio";
 600                 reg = <0x0 0x8b96000 0x0 0x1000>;
 601                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 602                 #address-cells = <1>;
 603                 #size-cells = <0>;
 604                 status = "disabled";
 605         };
 606
 607         /* WRIOP0: 0x8b8_0000, E-MDIO2: 0x1_7000 */
 608         emdio2: mdio@8b97000 {
 609                 compatible = "fsl,ls-mdio";
 610                 reg = <0x0 0x8b97000 0x0 0x1000>;
 611                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 612                 #address-cells = <1>;
 613                 #size-cells = <0>;
 614                 status = "disabled";
 615         };
 616         firmware {
 617                 optee {
 618                         compatible = "linaro,optee-tz";
 619                         method = "smc";
 620                 };
 621         };
 622 };