1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * NXP lx2160a SOC common device tree source
5 * Copyright 2018-2020 NXP
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "fsl,lx2160a";
13 interrupt-parent = <&gic>;
18 device_type = "memory";
19 reg = <0x00000000 0x80000000 0 0x80000000>;
20 /* DRAM space - 1, size : 2 GB DRAM */
24 compatible = "fixed-clock";
26 clock-frequency = <100000000>;
27 clock-output-names = "sysclk";
30 clockgen: clocking@1300000 {
31 compatible = "fsl,ls2080a-clockgen";
32 reg = <0 0x1300000 0 0xa0000>;
37 gic: interrupt-controller@6000000 {
38 compatible = "arm,gic-v3";
39 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
40 <0x0 0x06200000 0 0x100000>; /* GICR */
41 #interrupt-cells = <3>;
43 interrupts = <1 9 0x4>;
47 compatible = "arm,armv8-timer";
48 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
49 <1 14 0x8>, /* Physical NS PPI, active-low */
50 <1 11 0x8>, /* Virtual PPI, active-low */
51 <1 10 0x8>; /* Hypervisor PPI, active-low */
54 fspi: flexspi@20c0000 {
55 compatible = "nxp,lx2160a-fspi";
58 reg = <0x0 0x20c0000 0x0 0x10000>,
59 <0x0 0x20000000 0x0 0x10000000>;
60 reg-names = "fspi_base", "fspi_mmap";
61 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
62 clock-names = "fspi_en", "fspi";
63 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
68 compatible = "fsl,vf610-i2c";
71 reg = <0x0 0x2000000 0x0 0x10000>;
72 interrupts = <0 34 4>;
73 scl-gpio = <&gpio2 15 0>;
78 compatible = "fsl,vf610-i2c";
81 reg = <0x0 0x2010000 0x0 0x10000>;
82 interrupts = <0 34 4>;
87 compatible = "fsl,vf610-i2c";
90 reg = <0x0 0x2020000 0x0 0x10000>;
91 interrupts = <0 35 4>;
96 compatible = "fsl,vf610-i2c";
99 reg = <0x0 0x2030000 0x0 0x10000>;
100 interrupts = <0 35 4>;
105 compatible = "fsl,vf610-i2c";
106 #address-cells = <1>;
108 reg = <0x0 0x2040000 0x0 0x10000>;
109 interrupts = <0 74 4>;
110 scl-gpio = <&gpio2 16 0>;
115 compatible = "fsl,vf610-i2c";
116 #address-cells = <1>;
118 reg = <0x0 0x2050000 0x0 0x10000>;
119 interrupts = <0 74 4>;
124 compatible = "fsl,vf610-i2c";
125 #address-cells = <1>;
127 reg = <0x0 0x2060000 0x0 0x10000>;
128 interrupts = <0 75 4>;
133 compatible = "fsl,vf610-i2c";
134 #address-cells = <1>;
136 reg = <0x0 0x2070000 0x0 0x10000>;
137 interrupts = <0 75 4>;
141 uart0: serial@21c0000 {
142 compatible = "arm,pl011";
143 reg = <0x0 0x21c0000 0x0 0x1000>;
144 clocks = <&clockgen 4 0>;
148 uart1: serial@21d0000 {
149 compatible = "arm,pl011";
150 reg = <0x0 0x21d0000 0x0 0x1000>;
151 clocks = <&clockgen 4 0>;
155 uart2: serial@21e0000 {
156 compatible = "arm,pl011";
157 reg = <0x0 0x21e0000 0x0 0x1000>;
158 clocks = <&clockgen 4 0>;
162 uart3: serial@21f0000 {
163 compatible = "arm,pl011";
164 reg = <0x0 0x21f0000 0x0 0x1000>;
165 clocks = <&clockgen 4 0>;
169 dspi0: dspi@2100000 {
170 compatible = "fsl,vf610-dspi";
171 #address-cells = <1>;
173 reg = <0x0 0x2100000 0x0 0x10000>;
174 interrupts = <0 26 0x4>; /* Level high type */
178 dspi1: dspi@2110000 {
179 compatible = "fsl,vf610-dspi";
180 #address-cells = <1>;
182 reg = <0x0 0x2110000 0x0 0x10000>;
183 interrupts = <0 26 0x4>; /* Level high type */
187 dspi2: dspi@2120000 {
188 compatible = "fsl,vf610-dspi";
189 #address-cells = <1>;
191 reg = <0x0 0x2120000 0x0 0x10000>;
192 interrupts = <0 241 0x4>; /* Level high type */
196 gpio2: gpio@2320000 {
197 compatible = "fsl,qoriq-gpio";
198 reg = <0x0 0x2320000 0x0 0x10000>;
199 interrupts = <0 37 4>;
203 interrupt-controller;
204 #interrupt-cells = <2>;
208 compatible = "arm,sbsa-gwdt";
209 reg = <0x0 0x23a0000 0 0x1000>,
210 <0x0 0x2390000 0 0x1000>;
215 compatible = "fsl,layerscape-dwc3";
216 reg = <0x0 0x3100000 0x0 0x10000>;
217 interrupts = <0 80 0x4>; /* Level high type */
222 compatible = "fsl,layerscape-dwc3";
223 reg = <0x0 0x3110000 0x0 0x10000>;
224 interrupts = <0 81 0x4>; /* Level high type */
228 esdhc0: esdhc@2140000 {
229 compatible = "fsl,esdhc";
230 reg = <0x0 0x2140000 0x0 0x10000>;
231 interrupts = <0 28 0x4>; /* Level high type */
232 clocks = <&clockgen 4 1>;
233 voltage-ranges = <1800 1800 3300 3300>;
240 esdhc1: esdhc@2150000 {
241 compatible = "fsl,esdhc";
242 reg = <0x0 0x2150000 0x0 0x10000>;
243 interrupts = <0 63 0x4>; /* Level high type */
244 clocks = <&clockgen 4 1>;
245 voltage-ranges = <1800 1800 3300 3300>;
253 sata0: sata@3200000 {
254 compatible = "fsl,ls2080a-ahci";
255 reg = <0x0 0x3200000 0x0 0x10000>;
256 interrupts = <0 133 4>;
257 clocks = <&clockgen 4 3>;
262 sata1: sata@3210000 {
263 compatible = "fsl,ls2080a-ahci";
264 reg = <0x0 0x3210000 0x0 0x10000>;
265 interrupts = <0 136 4>;
266 clocks = <&clockgen 4 3>;
271 sata2: sata@3220000 {
272 compatible = "fsl,ls2080a-ahci";
273 reg = <0x0 0x3220000 0x0 0x10000>;
274 interrupts = <0 97 4>;
275 clocks = <&clockgen 4 3>;
280 sata3: sata@3230000 {
281 compatible = "fsl,ls2080a-ahci";
282 reg = <0x0 0x3230000 0x0 0x10000>;
283 interrupts = <0 100 4>;
284 clocks = <&clockgen 4 3>;
290 compatible = "fsl,lx2160a-pcie";
291 reg = <0x00 0x03400000 0x0 0x80000 /* PAB registers */
292 0x00 0x03480000 0x0 0x40000 /* LUT registers */
293 0x00 0x034c0000 0x0 0x40000 /* PF control registers */
294 0x80 0x00000000 0x0 0x2000>; /* configuration space */
295 reg-names = "ccsr", "lut", "pf_ctrl", "config";
296 #address-cells = <3>;
299 bus-range = <0x0 0xff>;
300 ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
304 compatible = "fsl,lx2160a-pcie";
305 reg = <0x00 0x03500000 0x0 0x80000 /* PAB registers */
306 0x00 0x03580000 0x0 0x40000 /* LUT registers */
307 0x00 0x035c0000 0x0 0x40000 /* PF control registers */
308 0x88 0x00000000 0x0 0x2000>; /* configuration space */
309 reg-names = "ccsr", "lut", "pf_ctrl", "config";
310 #address-cells = <3>;
314 bus-range = <0x0 0xff>;
315 ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>;
319 compatible = "fsl,lx2160a-pcie";
320 reg = <0x00 0x03600000 0x0 0x80000 /* PAB registers */
321 0x00 0x03680000 0x0 0x40000 /* LUT registers */
322 0x00 0x036c0000 0x0 0x40000 /* PF control registers */
323 0x90 0x00000000 0x0 0x2000>; /* configuration space */
324 reg-names = "ccsr", "lut", "pf_ctrl", "config";
325 #address-cells = <3>;
328 bus-range = <0x0 0xff>;
329 ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>;
333 compatible = "fsl,lx2160a-pcie";
334 reg = <0x00 0x03700000 0x0 0x80000 /* PAB registers */
335 0x00 0x03780000 0x0 0x40000 /* LUT registers */
336 0x00 0x037c0000 0x0 0x40000 /* PF control registers */
337 0x98 0x00000000 0x0 0x2000>; /* configuration space */
338 reg-names = "ccsr", "lut", "pf_ctrl", "config";
339 #address-cells = <3>;
342 bus-range = <0x0 0xff>;
343 ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>;
347 compatible = "fsl,lx2160a-pcie";
348 reg = <0x00 0x03800000 0x0 0x80000 /* PAB registers */
349 0x00 0x03880000 0x0 0x40000 /* LUT registers */
350 0x00 0x038c0000 0x0 0x40000 /* PF control registers */
351 0xa0 0x00000000 0x0 0x2000>; /* configuration space */
352 reg-names = "ccsr", "lut", "pf_ctrl", "config";
353 #address-cells = <3>;
356 bus-range = <0x0 0xff>;
357 ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>;
361 compatible = "fsl,lx2160a-pcie";
362 reg = <0x00 0x03900000 0x0 0x80000 /* PAB registers */
363 0x00 0x03980000 0x0 0x40000 /* LUT registers */
364 0x00 0x039c0000 0x0 0x40000 /* PF control registers */
365 0xa8 0x00000000 0x0 0x2000>; /* configuration space */
366 reg-names = "ccsr", "lut", "pf_ctrl", "config";
367 #address-cells = <3>;
370 bus-range = <0x0 0xff>;
371 ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>;
374 fsl_mc: fsl-mc@80c000000 {
375 compatible = "fsl,qoriq-mc", "simple-mfd";
376 reg = <0x00000008 0x0c000000 0 0x40>,
377 <0x00000000 0x08340000 0 0x40000>;
378 #address-cells = <3>;
382 * Region type 0x0 - MC portals
383 * Region type 0x1 - QBMAN portals
385 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
386 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
389 compatible = "simple-mfd";
390 #address-cells = <1>;
394 compatible = "fsl,qoriq-mc-dpmac";
400 compatible = "fsl,qoriq-mc-dpmac";
406 compatible = "fsl,qoriq-mc-dpmac";
412 compatible = "fsl,qoriq-mc-dpmac";
418 compatible = "fsl,qoriq-mc-dpmac";
424 compatible = "fsl,qoriq-mc-dpmac";
430 compatible = "fsl,qoriq-mc-dpmac";
436 compatible = "fsl,qoriq-mc-dpmac";
442 compatible = "fsl,qoriq-mc-dpmac";
448 compatible = "fsl,qoriq-mc-dpmac";
454 compatible = "fsl,qoriq-mc-dpmac";
460 compatible = "fsl,qoriq-mc-dpmac";
466 compatible = "fsl,qoriq-mc-dpmac";
472 compatible = "fsl,qoriq-mc-dpmac";
478 compatible = "fsl,qoriq-mc-dpmac";
484 compatible = "fsl,qoriq-mc-dpmac";
490 compatible = "fsl,qoriq-mc-dpmac";
496 compatible = "fsl,qoriq-mc-dpmac";
503 /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
504 emdio1: mdio@8b96000 {
505 compatible = "fsl,ls-mdio";
506 reg = <0x0 0x8b96000 0x0 0x1000>;
507 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
508 #address-cells = <1>;
513 /* WRIOP0: 0x8b8_0000, E-MDIO2: 0x1_7000 */
514 emdio2: mdio@8b97000 {
515 compatible = "fsl,ls-mdio";
516 reg = <0x0 0x8b97000 0x0 0x1000>;
517 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
518 #address-cells = <1>;
524 compatible = "linaro,optee-tz";