1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * NXP lx2160a SOC common device tree source
10 compatible = "fsl,lx2160a";
11 interrupt-parent = <&gic>;
16 device_type = "memory";
17 reg = <0x00000000 0x80000000 0 0x80000000>;
18 /* DRAM space - 1, size : 2 GB DRAM */
22 compatible = "fixed-clock";
24 clock-frequency = <100000000>;
25 clock-output-names = "sysclk";
28 clockgen: clocking@1300000 {
29 compatible = "fsl,ls2080a-clockgen";
30 reg = <0 0x1300000 0 0xa0000>;
35 gic: interrupt-controller@6000000 {
36 compatible = "arm,gic-v3";
37 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
38 <0x0 0x06200000 0 0x100000>; /* GICR */
39 #interrupt-cells = <3>;
41 interrupts = <1 9 0x4>;
45 compatible = "arm,armv8-timer";
46 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
47 <1 14 0x8>, /* Physical NS PPI, active-low */
48 <1 11 0x8>, /* Virtual PPI, active-low */
49 <1 10 0x8>; /* Hypervisor PPI, active-low */
53 compatible = "fsl,vf610-i2c";
56 reg = <0x0 0x2000000 0x0 0x10000>;
57 interrupts = <0 34 4>;
58 scl-gpio = <&gpio2 15 0>;
63 compatible = "fsl,vf610-i2c";
66 reg = <0x0 0x2010000 0x0 0x10000>;
67 interrupts = <0 34 4>;
72 compatible = "fsl,vf610-i2c";
75 reg = <0x0 0x2020000 0x0 0x10000>;
76 interrupts = <0 35 4>;
81 compatible = "fsl,vf610-i2c";
84 reg = <0x0 0x2030000 0x0 0x10000>;
85 interrupts = <0 35 4>;
90 compatible = "fsl,vf610-i2c";
93 reg = <0x0 0x2040000 0x0 0x10000>;
94 interrupts = <0 74 4>;
95 scl-gpio = <&gpio2 16 0>;
100 compatible = "fsl,vf610-i2c";
101 #address-cells = <1>;
103 reg = <0x0 0x2050000 0x0 0x10000>;
104 interrupts = <0 74 4>;
109 compatible = "fsl,vf610-i2c";
110 #address-cells = <1>;
112 reg = <0x0 0x2060000 0x0 0x10000>;
113 interrupts = <0 75 4>;
118 compatible = "fsl,vf610-i2c";
119 #address-cells = <1>;
121 reg = <0x0 0x2070000 0x0 0x10000>;
122 interrupts = <0 75 4>;
126 uart0: serial@21c0000 {
127 compatible = "arm,pl011";
128 reg = <0x0 0x21c0000 0x0 0x1000>;
129 clocks = <&clockgen 4 0>;
132 uart1: serial@21d0000 {
133 compatible = "arm,pl011";
134 reg = <0x0 0x21d0000 0x0 0x1000>;
135 clocks = <&clockgen 4 0>;
138 uart2: serial@21e0000 {
139 compatible = "arm,pl011";
140 reg = <0x0 0x21e0000 0x0 0x1000>;
141 clocks = <&clockgen 4 0>;
145 uart3: serial@21f0000 {
146 compatible = "arm,pl011";
147 reg = <0x0 0x21f0000 0x0 0x1000>;
148 clocks = <&clockgen 4 0>;
152 dspi0: dspi@2100000 {
153 compatible = "fsl,vf610-dspi";
154 #address-cells = <1>;
156 reg = <0x0 0x2100000 0x0 0x10000>;
157 interrupts = <0 26 0x4>; /* Level high type */
161 dspi1: dspi@2110000 {
162 compatible = "fsl,vf610-dspi";
163 #address-cells = <1>;
165 reg = <0x0 0x2110000 0x0 0x10000>;
166 interrupts = <0 26 0x4>; /* Level high type */
170 dspi2: dspi@2120000 {
171 compatible = "fsl,vf610-dspi";
172 #address-cells = <1>;
174 reg = <0x0 0x2120000 0x0 0x10000>;
175 interrupts = <0 241 0x4>; /* Level high type */
179 gpio2: gpio@2320000 {
180 compatible = "fsl,qoriq-gpio";
181 reg = <0x0 0x2320000 0x0 0x10000>;
182 interrupts = <0 37 4>;
186 interrupt-controller;
187 #interrupt-cells = <2>;
191 compatible = "fsl,layerscape-dwc3";
192 reg = <0x0 0x3100000 0x0 0x10000>;
193 interrupts = <0 80 0x4>; /* Level high type */
198 compatible = "fsl,layerscape-dwc3";
199 reg = <0x0 0x3110000 0x0 0x10000>;
200 interrupts = <0 81 0x4>; /* Level high type */
204 esdhc0: esdhc@2140000 {
205 compatible = "fsl,esdhc";
206 reg = <0x0 0x2140000 0x0 0x10000>;
207 interrupts = <0 28 0x4>; /* Level high type */
208 clocks = <&clockgen 4 1>;
209 voltage-ranges = <1800 1800 3300 3300>;
216 esdhc1: esdhc@2150000 {
217 compatible = "fsl,esdhc";
218 reg = <0x0 0x2150000 0x0 0x10000>;
219 interrupts = <0 63 0x4>; /* Level high type */
220 clocks = <&clockgen 4 1>;
221 voltage-ranges = <1800 1800 3300 3300>;
229 sata0: sata@3200000 {
230 compatible = "fsl,ls2080a-ahci";
231 reg = <0x0 0x3200000 0x0 0x10000>;
232 interrupts = <0 133 4>;
233 clocks = <&clockgen 4 3>;
238 sata1: sata@3210000 {
239 compatible = "fsl,ls2080a-ahci";
240 reg = <0x0 0x3210000 0x0 0x10000>;
241 interrupts = <0 136 4>;
242 clocks = <&clockgen 4 3>;
247 sata2: sata@3220000 {
248 compatible = "fsl,ls2080a-ahci";
249 reg = <0x0 0x3220000 0x0 0x10000>;
250 interrupts = <0 97 4>;
251 clocks = <&clockgen 4 3>;
256 sata3: sata@3230000 {
257 compatible = "fsl,ls2080a-ahci";
258 reg = <0x0 0x3230000 0x0 0x10000>;
259 interrupts = <0 100 4>;
260 clocks = <&clockgen 4 3>;
266 compatible = "fsl,lx2160a-pcie";
267 reg = <0x00 0x03400000 0x0 0x80000 /* PAB registers */
268 0x00 0x03480000 0x0 0x40000 /* LUT registers */
269 0x00 0x034c0000 0x0 0x40000 /* PF control registers */
270 0x80 0x00000000 0x0 0x1000>; /* configuration space */
271 reg-names = "ccsr", "lut", "pf_ctrl", "config";
272 #address-cells = <3>;
275 bus-range = <0x0 0xff>;
276 ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
280 compatible = "fsl,lx2160a-pcie";
281 reg = <0x00 0x03500000 0x0 0x80000 /* PAB registers */
282 0x00 0x03580000 0x0 0x40000 /* LUT registers */
283 0x00 0x035c0000 0x0 0x40000 /* PF control registers */
284 0x88 0x00000000 0x0 0x1000>; /* configuration space */
285 reg-names = "ccsr", "lut", "pf_ctrl", "config";
286 #address-cells = <3>;
290 bus-range = <0x0 0xff>;
291 ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>;
295 compatible = "fsl,lx2160a-pcie";
296 reg = <0x00 0x03600000 0x0 0x80000 /* PAB registers */
297 0x00 0x03680000 0x0 0x40000 /* LUT registers */
298 0x00 0x036c0000 0x0 0x40000 /* PF control registers */
299 0x90 0x00000000 0x0 0x1000>; /* configuration space */
300 reg-names = "ccsr", "lut", "pf_ctrl", "config";
301 #address-cells = <3>;
304 bus-range = <0x0 0xff>;
305 ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>;
309 compatible = "fsl,lx2160a-pcie";
310 reg = <0x00 0x03700000 0x0 0x80000 /* PAB registers */
311 0x00 0x03780000 0x0 0x40000 /* LUT registers */
312 0x00 0x037c0000 0x0 0x40000 /* PF control registers */
313 0x98 0x00000000 0x0 0x1000>; /* configuration space */
314 reg-names = "ccsr", "lut", "pf_ctrl", "config";
315 #address-cells = <3>;
318 bus-range = <0x0 0xff>;
319 ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>;
323 compatible = "fsl,lx2160a-pcie";
324 reg = <0x00 0x03800000 0x0 0x80000 /* PAB registers */
325 0x00 0x03880000 0x0 0x40000 /* LUT registers */
326 0x00 0x038c0000 0x0 0x40000 /* PF control registers */
327 0xa0 0x00000000 0x0 0x1000>; /* configuration space */
328 reg-names = "ccsr", "lut", "pf_ctrl", "config";
329 #address-cells = <3>;
332 bus-range = <0x0 0xff>;
333 ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>;
337 compatible = "fsl,lx2160a-pcie";
338 reg = <0x00 0x03900000 0x0 0x80000 /* PAB registers */
339 0x00 0x03980000 0x0 0x40000 /* LUT registers */
340 0x00 0x039c0000 0x0 0x40000 /* PF control registers */
341 0xa8 0x00000000 0x0 0x1000>; /* configuration space */
342 reg-names = "ccsr", "lut", "pf_ctrl", "config";
343 #address-cells = <3>;
346 bus-range = <0x0 0xff>;
347 ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>;