arch/arm/dts/fsl-lx2160a.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * NXP lx2160a SOC common device tree source
   4  *
   5  * Copyright 2018-2020 NXP
   6  *
   7  */
   8
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10
  11 / {
  12         compatible = "fsl,lx2160a";
  13         interrupt-parent = <&gic>;
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         memory@80000000 {
  18                 device_type = "memory";
  19                 reg = <0x00000000 0x80000000 0 0x80000000>;
  20                       /* DRAM space - 1, size : 2 GB DRAM */
  21         };
  22
  23         sysclk: sysclk {
  24                 compatible = "fixed-clock";
  25                 #clock-cells = <0>;
  26                 clock-frequency = <100000000>;
  27                 clock-output-names = "sysclk";
  28         };
  29
  30         clockgen: clocking@1300000 {
  31                 compatible = "fsl,ls2080a-clockgen";
  32                 reg = <0 0x1300000 0 0xa0000>;
  33                 #clock-cells = <2>;
  34                 clocks = <&sysclk>;
  35         };
  36
  37         gic: interrupt-controller@6000000 {
  38                 compatible = "arm,gic-v3";
  39                 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
  40                       <0x0 0x06200000 0 0x100000>; /* GICR */
  41                 #interrupt-cells = <3>;
  42                 interrupt-controller;
  43                 interrupts = <1 9 0x4>;
  44         };
  45
  46         timer {
  47                 compatible = "arm,armv8-timer";
  48                 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
  49                              <1 14 0x8>, /* Physical NS PPI, active-low */
  50                              <1 11 0x8>, /* Virtual PPI, active-low */
  51                              <1 10 0x8>; /* Hypervisor PPI, active-low */
  52         };
  53
  54         fspi: flexspi@20c0000 {
  55                 compatible = "nxp,lx2160a-fspi";
  56                 #address-cells = <1>;
  57                 #size-cells = <0>;
  58                 reg = <0x0 0x20c0000 0x0 0x10000>,
  59                         <0x0 0x20000000 0x0 0x10000000>;
  60                 reg-names = "fspi_base", "fspi_mmap";
  61                 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
  62                 clock-names = "fspi_en", "fspi";
  63                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  64                 status = "disabled";
  65         };
  66
  67         i2c0: i2c@2000000 {
  68                 compatible = "fsl,vf610-i2c";
  69                 #address-cells = <1>;
  70                 #size-cells = <0>;
  71                 reg = <0x0 0x2000000 0x0 0x10000>;
  72                 interrupts = <0 34 4>;
  73                 scl-gpio = <&gpio2 15 0>;
  74                 status = "disabled";
  75         };
  76
  77         i2c1: i2c@2010000 {
  78                 compatible = "fsl,vf610-i2c";
  79                 #address-cells = <1>;
  80                 #size-cells = <0>;
  81                 reg = <0x0 0x2010000 0x0 0x10000>;
  82                 interrupts = <0 34 4>;
  83                 status = "disabled";
  84         };
  85
  86         i2c2: i2c@2020000 {
  87                 compatible = "fsl,vf610-i2c";
  88                 #address-cells = <1>;
  89                 #size-cells = <0>;
  90                 reg = <0x0 0x2020000 0x0 0x10000>;
  91                 interrupts = <0 35 4>;
  92                 status = "disabled";
  93         };
  94
  95         i2c3: i2c@2030000 {
  96                 compatible = "fsl,vf610-i2c";
  97                 #address-cells = <1>;
  98                 #size-cells = <0>;
  99                 reg = <0x0 0x2030000 0x0 0x10000>;
 100                 interrupts = <0 35 4>;
 101                 status = "disabled";
 102         };
 103
 104         i2c4: i2c@2040000 {
 105                 compatible = "fsl,vf610-i2c";
 106                 #address-cells = <1>;
 107                 #size-cells = <0>;
 108                 reg = <0x0 0x2040000 0x0 0x10000>;
 109                 interrupts = <0 74 4>;
 110                 scl-gpio = <&gpio2 16 0>;
 111                 status = "disabled";
 112         };
 113
 114         i2c5: i2c@2050000 {
 115                 compatible = "fsl,vf610-i2c";
 116                 #address-cells = <1>;
 117                 #size-cells = <0>;
 118                 reg = <0x0 0x2050000 0x0 0x10000>;
 119                 interrupts = <0 74 4>;
 120                 status = "disabled";
 121         };
 122
 123         i2c6: i2c@2060000 {
 124                 compatible = "fsl,vf610-i2c";
 125                 #address-cells = <1>;
 126                 #size-cells = <0>;
 127                 reg = <0x0 0x2060000 0x0 0x10000>;
 128                 interrupts = <0 75 4>;
 129                 status = "disabled";
 130         };
 131
 132         i2c7: i2c@2070000 {
 133                 compatible = "fsl,vf610-i2c";
 134                 #address-cells = <1>;
 135                 #size-cells = <0>;
 136                 reg = <0x0 0x2070000 0x0 0x10000>;
 137                 interrupts = <0 75 4>;
 138                 status = "disabled";
 139         };
 140
 141         uart0: serial@21c0000 {
 142                 compatible = "arm,pl011";
 143                 reg = <0x0 0x21c0000 0x0 0x1000>;
 144                 clocks = <&clockgen 4 0>;
 145                 status = "disabled";
 146         };
 147
 148         uart1: serial@21d0000 {
 149                 compatible = "arm,pl011";
 150                 reg = <0x0 0x21d0000 0x0 0x1000>;
 151                 clocks = <&clockgen 4 0>;
 152                 status = "disabled";
 153         };
 154
 155         uart2: serial@21e0000 {
 156                 compatible = "arm,pl011";
 157                 reg = <0x0 0x21e0000 0x0 0x1000>;
 158                 clocks = <&clockgen 4 0>;
 159                 status = "disabled";
 160         };
 161
 162         uart3: serial@21f0000 {
 163                 compatible = "arm,pl011";
 164                 reg = <0x0 0x21f0000 0x0 0x1000>;
 165                 clocks = <&clockgen 4 0>;
 166                 status = "disabled";
 167         };
 168
 169         dspi0: dspi@2100000 {
 170                 compatible = "fsl,vf610-dspi";
 171                 #address-cells = <1>;
 172                 #size-cells = <0>;
 173                 reg = <0x0 0x2100000 0x0 0x10000>;
 174                 interrupts = <0 26 0x4>; /* Level high type */
 175                 spi-num-chipselects = <6>;
 176         };
 177
 178         dspi1: dspi@2110000 {
 179                 compatible = "fsl,vf610-dspi";
 180                 #address-cells = <1>;
 181                 #size-cells = <0>;
 182                 reg = <0x0 0x2110000 0x0 0x10000>;
 183                 interrupts = <0 26 0x4>; /* Level high type */
 184                 spi-num-chipselects = <6>;
 185         };
 186
 187         dspi2: dspi@2120000 {
 188                 compatible = "fsl,vf610-dspi";
 189                 #address-cells = <1>;
 190                 #size-cells = <0>;
 191                 reg = <0x0 0x2120000 0x0 0x10000>;
 192                 interrupts = <0 241 0x4>; /* Level high type */
 193                 spi-num-chipselects = <6>;
 194         };
 195
 196         gpio0: gpio@2300000 {
 197                 compatible = "fsl,qoriq-gpio";
 198                 reg = <0x0 0x2300000 0x0 0x10000>;
 199                 interrupts = <0 36 4>;
 200                 gpio-controller;
 201                 little-endian;
 202                 #gpio-cells = <2>;
 203                 interrupt-controller;
 204                 #interrupt-cells = <2>;
 205         };
 206
 207         gpio1: gpio@2310000 {
 208                 compatible = "fsl,qoriq-gpio";
 209                 reg = <0x0 0x2310000 0x0 0x10000>;
 210                 interrupts = <0 36 4>;
 211                 gpio-controller;
 212                 little-endian;
 213                 #gpio-cells = <2>;
 214                 interrupt-controller;
 215                 #interrupt-cells = <2>;
 216         };
 217
 218         gpio2: gpio@2320000 {
 219                 compatible = "fsl,qoriq-gpio";
 220                 reg = <0x0 0x2320000 0x0 0x10000>;
 221                 interrupts = <0 37 4>;
 222                 gpio-controller;
 223                 little-endian;
 224                 #gpio-cells = <2>;
 225                 interrupt-controller;
 226                 #interrupt-cells = <2>;
 227         };
 228
 229         gpio3: gpio@2330000 {
 230                 compatible = "fsl,qoriq-gpio";
 231                 reg = <0x0 0x2330000 0x0 0x10000>;
 232                 interrupts = <0 37 4>;
 233                 gpio-controller;
 234                 little-endian;
 235                 #gpio-cells = <2>;
 236                 interrupt-controller;
 237                 #interrupt-cells = <2>;
 238         };
 239
 240         watchdog@23a0000 {
 241                 compatible = "arm,sbsa-gwdt";
 242                 reg = <0x0 0x23a0000 0 0x1000>,
 243                       <0x0 0x2390000 0 0x1000>;
 244                 timeout-sec = <30>;
 245         };
 246
 247         usb0: usb3@3100000 {
 248                 compatible = "fsl,layerscape-dwc3";
 249                 reg = <0x0 0x3100000 0x0 0x10000>;
 250                 interrupts = <0 80 0x4>; /* Level high type */
 251                 dr_mode = "host";
 252         };
 253
 254         usb1: usb3@3110000 {
 255                 compatible = "fsl,layerscape-dwc3";
 256                 reg = <0x0 0x3110000 0x0 0x10000>;
 257                 interrupts = <0 81 0x4>; /* Level high type */
 258                 dr_mode = "host";
 259         };
 260
 261         esdhc0: esdhc@2140000 {
 262                 compatible = "fsl,esdhc";
 263                 reg = <0x0 0x2140000 0x0 0x10000>;
 264                 interrupts = <0 28 0x4>; /* Level high type */
 265                 clocks = <&clockgen 4 1>;
 266                 voltage-ranges = <1800 1800 3300 3300>;
 267                 sdhci,auto-cmd12;
 268                 little-endian;
 269                 bus-width = <4>;
 270                 status = "disabled";
 271         };
 272
 273         esdhc1: esdhc@2150000 {
 274                 compatible = "fsl,esdhc";
 275                 reg = <0x0 0x2150000 0x0 0x10000>;
 276                 interrupts = <0 63 0x4>; /* Level high type */
 277                 clocks = <&clockgen 4 1>;
 278                 voltage-ranges = <1800 1800 3300 3300>;
 279                 sdhci,auto-cmd12;
 280                 non-removable;
 281                 little-endian;
 282                 bus-width = <4>;
 283                 status = "disabled";
 284         };
 285
 286         sata0: sata@3200000 {
 287                         compatible = "fsl,ls2080a-ahci";
 288                         reg = <0x0 0x3200000 0x0 0x10000>;
 289                         interrupts = <0 133 4>;
 290                         clocks = <&clockgen 4 3>;
 291                         status = "disabled";
 292
 293         };
 294
 295         sata1: sata@3210000 {
 296                         compatible = "fsl,ls2080a-ahci";
 297                         reg = <0x0 0x3210000 0x0 0x10000>;
 298                         interrupts = <0 136 4>;
 299                         clocks = <&clockgen 4 3>;
 300                         status = "disabled";
 301
 302         };
 303
 304         sata2: sata@3220000 {
 305                         compatible = "fsl,ls2080a-ahci";
 306                         reg = <0x0 0x3220000 0x0 0x10000>;
 307                         interrupts = <0 97 4>;
 308                         clocks = <&clockgen 4 3>;
 309                         status = "disabled";
 310
 311         };
 312
 313         sata3: sata@3230000 {
 314                         compatible = "fsl,ls2080a-ahci";
 315                         reg = <0x0 0x3230000 0x0 0x10000>;
 316                         interrupts = <0 100 4>;
 317                         clocks = <&clockgen 4 3>;
 318                         status = "disabled";
 319
 320         };
 321
 322         pcie1: pcie@3400000 {
 323                 compatible = "fsl,lx2160a-pcie";
 324                 reg = <0x00 0x03400000 0x0 0x80000   /* PAB registers */
 325                        0x00 0x03480000 0x0 0x40000   /* LUT registers */
 326                        0x00 0x034c0000 0x0 0x40000   /* PF control registers */
 327                        0x80 0x00000000 0x0 0x2000>; /* configuration space */
 328                 reg-names = "ccsr", "lut", "pf_ctrl", "config";
 329                 #address-cells = <3>;
 330                 #size-cells = <2>;
 331                 device_type = "pci";
 332                 bus-range = <0x0 0xff>;
 333                 ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000   /* downstream I/O */
 334                           0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 335         };
 336
 337         pcie2: pcie@3500000 {
 338                 compatible = "fsl,lx2160a-pcie";
 339                 reg = <0x00 0x03500000 0x0 0x80000   /* PAB registers */
 340                        0x00 0x03580000 0x0 0x40000   /* LUT registers */
 341                        0x00 0x035c0000 0x0 0x40000   /* PF control registers */
 342                        0x88 0x00000000 0x0 0x2000>; /* configuration space */
 343                 reg-names = "ccsr", "lut", "pf_ctrl", "config";
 344                 #address-cells = <3>;
 345                 #size-cells = <2>;
 346                 device_type = "pci";
 347                 num-lanes = <2>;
 348                 bus-range = <0x0 0xff>;
 349                 ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000   /* downstream I/O */
 350                           0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 351         };
 352
 353         pcie3: pcie@3600000 {
 354                 compatible = "fsl,lx2160a-pcie";
 355                 reg = <0x00 0x03600000 0x0 0x80000   /* PAB registers */
 356                        0x00 0x03680000 0x0 0x40000   /* LUT registers */
 357                        0x00 0x036c0000 0x0 0x40000   /* PF control registers */
 358                        0x90 0x00000000 0x0 0x2000>; /* configuration space */
 359                 reg-names = "ccsr", "lut", "pf_ctrl", "config";
 360                 #address-cells = <3>;
 361                 #size-cells = <2>;
 362                 device_type = "pci";
 363                 bus-range = <0x0 0xff>;
 364                 ranges = <0x81000000 0x0 0x00000000 0x90 0x00020000 0x0 0x00010000   /* downstream I/O */
 365                           0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 366         };
 367
 368         pcie4: pcie@3700000 {
 369                 compatible = "fsl,lx2160a-pcie";
 370                 reg = <0x00 0x03700000 0x0 0x80000   /* PAB registers */
 371                        0x00 0x03780000 0x0 0x40000   /* LUT registers */
 372                        0x00 0x037c0000 0x0 0x40000   /* PF control registers */
 373                        0x98 0x00000000 0x0 0x2000>; /* configuration space */
 374                 reg-names = "ccsr", "lut", "pf_ctrl", "config";
 375                 #address-cells = <3>;
 376                 #size-cells = <2>;
 377                 device_type = "pci";
 378                 bus-range = <0x0 0xff>;
 379                 ranges = <0x81000000 0x0 0x00000000 0x98 0x00020000 0x0 0x00010000   /* downstream I/O */
 380                           0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 381         };
 382
 383         pcie5: pcie@3800000 {
 384                 compatible = "fsl,lx2160a-pcie";
 385                 reg = <0x00 0x03800000 0x0 0x80000   /* PAB registers */
 386                        0x00 0x03880000 0x0 0x40000   /* LUT registers */
 387                        0x00 0x038c0000 0x0 0x40000   /* PF control registers */
 388                        0xa0 0x00000000 0x0 0x2000>; /* configuration space */
 389                 reg-names = "ccsr", "lut", "pf_ctrl", "config";
 390                 #address-cells = <3>;
 391                 #size-cells = <2>;
 392                 device_type = "pci";
 393                 bus-range = <0x0 0xff>;
 394                 ranges = <0x81000000 0x0 0x00000000 0xa0 0x00020000 0x0 0x00010000   /* downstream I/O */
 395                           0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 396         };
 397
 398         pcie6: pcie@3900000 {
 399                 compatible = "fsl,lx2160a-pcie";
 400                 reg = <0x00 0x03900000 0x0 0x80000   /* PAB registers */
 401                        0x00 0x03980000 0x0 0x40000   /* LUT registers */
 402                        0x00 0x039c0000 0x0 0x40000   /* PF control registers */
 403                        0xa8 0x00000000 0x0 0x2000>; /* configuration space */
 404                 reg-names = "ccsr", "lut", "pf_ctrl", "config";
 405                 #address-cells = <3>;
 406                 #size-cells = <2>;
 407                 device_type = "pci";
 408                 bus-range = <0x0 0xff>;
 409                 ranges = <0x81000000 0x0 0x00000000 0xa8 0x00020000 0x0 0x00010000   /* downstream I/O */
 410                           0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 411         };
 412
 413         fsl_mc: fsl-mc@80c000000 {
 414                 compatible = "fsl,qoriq-mc", "simple-mfd";
 415                 reg = <0x00000008 0x0c000000 0 0x40>,
 416                       <0x00000000 0x08340000 0 0x40000>;
 417                 #address-cells = <3>;
 418                 #size-cells = <1>;
 419
 420                 /*
 421                  * Region type 0x0 - MC portals
 422                  * Region type 0x1 - QBMAN portals
 423                  */
 424                 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
 425                           0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
 426
 427                 dpmacs {
 428                         compatible = "simple-mfd";
 429                         #address-cells = <1>;
 430                         #size-cells = <0>;
 431
 432                         dpmac1: dpmac@1 {
 433                                 compatible = "fsl,qoriq-mc-dpmac";
 434                                 reg = <0x1>;
 435                                 status = "disabled";
 436                         };
 437
 438                         dpmac2: dpmac@2 {
 439                                 compatible = "fsl,qoriq-mc-dpmac";
 440                                 reg = <0x2>;
 441                                 status = "disabled";
 442                         };
 443
 444                         dpmac3: dpmac@3 {
 445                                 compatible = "fsl,qoriq-mc-dpmac";
 446                                 reg = <0x3>;
 447                                 status = "disabled";
 448                         };
 449
 450                         dpmac4: dpmac@4 {
 451                                 compatible = "fsl,qoriq-mc-dpmac";
 452                                 reg = <0x4>;
 453                                 status = "disabled";
 454                         };
 455
 456                         dpmac5: dpmac@5 {
 457                                 compatible = "fsl,qoriq-mc-dpmac";
 458                                 reg = <0x5>;
 459                                 status = "disabled";
 460                         };
 461
 462                         dpmac6: dpmac@6 {
 463                                 compatible = "fsl,qoriq-mc-dpmac";
 464                                 reg = <0x6>;
 465                                 status = "disabled";
 466                         };
 467
 468                         dpmac7: dpmac@7 {
 469                                 compatible = "fsl,qoriq-mc-dpmac";
 470                                 reg = <0x7>;
 471                                 status = "disabled";
 472                         };
 473
 474                         dpmac8: dpmac@8 {
 475                                 compatible = "fsl,qoriq-mc-dpmac";
 476                                 reg = <0x8>;
 477                                 status = "disabled";
 478                         };
 479
 480                         dpmac9: dpmac@9 {
 481                                 compatible = "fsl,qoriq-mc-dpmac";
 482                                 reg = <0x9>;
 483                                 status = "disabled";
 484                         };
 485
 486                         dpmac10: dpmac@a {
 487                                 compatible = "fsl,qoriq-mc-dpmac";
 488                                 reg = <0xa>;
 489                                 status = "disabled";
 490                         };
 491
 492                         dpmac11: dpmac@b {
 493                                 compatible = "fsl,qoriq-mc-dpmac";
 494                                 reg = <0xb>;
 495                                 status = "disabled";
 496                         };
 497
 498                         dpmac12: dpmac@c {
 499                                 compatible = "fsl,qoriq-mc-dpmac";
 500                                 reg = <0xc>;
 501                                 status = "disabled";
 502                         };
 503
 504                         dpmac13: dpmac@d {
 505                                 compatible = "fsl,qoriq-mc-dpmac";
 506                                 reg = <0xd>;
 507                                 status = "disabled";
 508                         };
 509
 510                         dpmac14: dpmac@e {
 511                                 compatible = "fsl,qoriq-mc-dpmac";
 512                                 reg = <0xe>;
 513                                 status = "disabled";
 514                         };
 515
 516                         dpmac15: dpmac@f {
 517                                 compatible = "fsl,qoriq-mc-dpmac";
 518                                 reg = <0xf>;
 519                                 status = "disabled";
 520                         };
 521
 522                         dpmac16: dpmac@10 {
 523                                 compatible = "fsl,qoriq-mc-dpmac";
 524                                 reg = <0x10>;
 525                                 status = "disabled";
 526                         };
 527
 528                         dpmac17: dpmac@11 {
 529                                 compatible = "fsl,qoriq-mc-dpmac";
 530                                 reg = <0x11>;
 531                                 status = "disabled";
 532                         };
 533
 534                         dpmac18: dpmac@12 {
 535                                 compatible = "fsl,qoriq-mc-dpmac";
 536                                 reg = <0x12>;
 537                                 status = "disabled";
 538                         };
 539                 };
 540         };
 541
 542         /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
 543         emdio1: mdio@8b96000 {
 544                 compatible = "fsl,ls-mdio";
 545                 reg = <0x0 0x8b96000 0x0 0x1000>;
 546                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 547                 #address-cells = <1>;
 548                 #size-cells = <0>;
 549                 status = "disabled";
 550         };
 551
 552         /* WRIOP0: 0x8b8_0000, E-MDIO2: 0x1_7000 */
 553         emdio2: mdio@8b97000 {
 554                 compatible = "fsl,ls-mdio";
 555                 reg = <0x0 0x8b97000 0x0 0x1000>;
 556                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 557                 #address-cells = <1>;
 558                 #size-cells = <0>;
 559                 status = "disabled";
 560         };
 561         firmware {
 562                 optee {
 563                         compatible = "linaro,optee-tz";
 564                         method = "smc";
 565                 };
 566         };
 567 };