arch/arm/dts/fsl-lx2160a.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * NXP lx2160a SOC common device tree source
   4  *
   5  * Copyright 2018-2020 NXP
   6  *
   7  */
   8
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10
  11 / {
  12         compatible = "fsl,lx2160a";
  13         interrupt-parent = <&gic>;
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         memory@80000000 {
  18                 device_type = "memory";
  19                 reg = <0x00000000 0x80000000 0 0x80000000>;
  20                       /* DRAM space - 1, size : 2 GB DRAM */
  21         };
  22
  23         sysclk: sysclk {
  24                 compatible = "fixed-clock";
  25                 #clock-cells = <0>;
  26                 clock-frequency = <100000000>;
  27                 clock-output-names = "sysclk";
  28         };
  29
  30         clockgen: clocking@1300000 {
  31                 compatible = "fsl,ls2080a-clockgen";
  32                 reg = <0 0x1300000 0 0xa0000>;
  33                 #clock-cells = <2>;
  34                 clocks = <&sysclk>;
  35         };
  36
  37         gic: interrupt-controller@6000000 {
  38                 compatible = "arm,gic-v3";
  39                 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
  40                       <0x0 0x06200000 0 0x100000>; /* GICR */
  41                 #interrupt-cells = <3>;
  42                 interrupt-controller;
  43                 interrupts = <1 9 0x4>;
  44         };
  45
  46         gic_lpi_base: syscon@0x80000000 {
  47                 compatible = "gic-lpi-base";
  48                 reg = <0x0 0x80000000 0x0 0x200000>;
  49                 max-gic-redistributors = <16>;
  50         };
  51
  52         timer {
  53                 compatible = "arm,armv8-timer";
  54                 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
  55                              <1 14 0x8>, /* Physical NS PPI, active-low */
  56                              <1 11 0x8>, /* Virtual PPI, active-low */
  57                              <1 10 0x8>; /* Hypervisor PPI, active-low */
  58         };
  59
  60         fspi: flexspi@20c0000 {
  61                 compatible = "nxp,lx2160a-fspi";
  62                 #address-cells = <1>;
  63                 #size-cells = <0>;
  64                 reg = <0x0 0x20c0000 0x0 0x10000>,
  65                         <0x0 0x20000000 0x0 0x10000000>;
  66                 reg-names = "fspi_base", "fspi_mmap";
  67                 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
  68                 clock-names = "fspi_en", "fspi";
  69                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  70                 status = "disabled";
  71         };
  72
  73         i2c0: i2c@2000000 {
  74                 compatible = "fsl,vf610-i2c";
  75                 #address-cells = <1>;
  76                 #size-cells = <0>;
  77                 reg = <0x0 0x2000000 0x0 0x10000>;
  78                 interrupts = <0 34 4>;
  79                 scl-gpio = <&gpio2 15 0>;
  80                 status = "disabled";
  81         };
  82
  83         i2c1: i2c@2010000 {
  84                 compatible = "fsl,vf610-i2c";
  85                 #address-cells = <1>;
  86                 #size-cells = <0>;
  87                 reg = <0x0 0x2010000 0x0 0x10000>;
  88                 interrupts = <0 34 4>;
  89                 status = "disabled";
  90         };
  91
  92         i2c2: i2c@2020000 {
  93                 compatible = "fsl,vf610-i2c";
  94                 #address-cells = <1>;
  95                 #size-cells = <0>;
  96                 reg = <0x0 0x2020000 0x0 0x10000>;
  97                 interrupts = <0 35 4>;
  98                 status = "disabled";
  99         };
 100
 101         i2c3: i2c@2030000 {
 102                 compatible = "fsl,vf610-i2c";
 103                 #address-cells = <1>;
 104                 #size-cells = <0>;
 105                 reg = <0x0 0x2030000 0x0 0x10000>;
 106                 interrupts = <0 35 4>;
 107                 status = "disabled";
 108         };
 109
 110         i2c4: i2c@2040000 {
 111                 compatible = "fsl,vf610-i2c";
 112                 #address-cells = <1>;
 113                 #size-cells = <0>;
 114                 reg = <0x0 0x2040000 0x0 0x10000>;
 115                 interrupts = <0 74 4>;
 116                 scl-gpio = <&gpio2 16 0>;
 117                 status = "disabled";
 118         };
 119
 120         i2c5: i2c@2050000 {
 121                 compatible = "fsl,vf610-i2c";
 122                 #address-cells = <1>;
 123                 #size-cells = <0>;
 124                 reg = <0x0 0x2050000 0x0 0x10000>;
 125                 interrupts = <0 74 4>;
 126                 status = "disabled";
 127         };
 128
 129         i2c6: i2c@2060000 {
 130                 compatible = "fsl,vf610-i2c";
 131                 #address-cells = <1>;
 132                 #size-cells = <0>;
 133                 reg = <0x0 0x2060000 0x0 0x10000>;
 134                 interrupts = <0 75 4>;
 135                 status = "disabled";
 136         };
 137
 138         i2c7: i2c@2070000 {
 139                 compatible = "fsl,vf610-i2c";
 140                 #address-cells = <1>;
 141                 #size-cells = <0>;
 142                 reg = <0x0 0x2070000 0x0 0x10000>;
 143                 interrupts = <0 75 4>;
 144                 status = "disabled";
 145         };
 146
 147         uart0: serial@21c0000 {
 148                 compatible = "arm,pl011";
 149                 reg = <0x0 0x21c0000 0x0 0x1000>;
 150                 clocks = <&clockgen 4 0>;
 151                 status = "disabled";
 152         };
 153
 154         uart1: serial@21d0000 {
 155                 compatible = "arm,pl011";
 156                 reg = <0x0 0x21d0000 0x0 0x1000>;
 157                 clocks = <&clockgen 4 0>;
 158                 status = "disabled";
 159         };
 160
 161         uart2: serial@21e0000 {
 162                 compatible = "arm,pl011";
 163                 reg = <0x0 0x21e0000 0x0 0x1000>;
 164                 clocks = <&clockgen 4 0>;
 165                 status = "disabled";
 166         };
 167
 168         uart3: serial@21f0000 {
 169                 compatible = "arm,pl011";
 170                 reg = <0x0 0x21f0000 0x0 0x1000>;
 171                 clocks = <&clockgen 4 0>;
 172                 status = "disabled";
 173         };
 174
 175         dspi0: dspi@2100000 {
 176                 compatible = "fsl,vf610-dspi";
 177                 #address-cells = <1>;
 178                 #size-cells = <0>;
 179                 reg = <0x0 0x2100000 0x0 0x10000>;
 180                 interrupts = <0 26 0x4>; /* Level high type */
 181                 num-cs = <6>;
 182         };
 183
 184         dspi1: dspi@2110000 {
 185                 compatible = "fsl,vf610-dspi";
 186                 #address-cells = <1>;
 187                 #size-cells = <0>;
 188                 reg = <0x0 0x2110000 0x0 0x10000>;
 189                 interrupts = <0 26 0x4>; /* Level high type */
 190                 num-cs = <6>;
 191         };
 192
 193         dspi2: dspi@2120000 {
 194                 compatible = "fsl,vf610-dspi";
 195                 #address-cells = <1>;
 196                 #size-cells = <0>;
 197                 reg = <0x0 0x2120000 0x0 0x10000>;
 198                 interrupts = <0 241 0x4>; /* Level high type */
 199                 num-cs = <6>;
 200         };
 201
 202         gpio2: gpio@2320000 {
 203                 compatible = "fsl,qoriq-gpio";
 204                 reg = <0x0 0x2320000 0x0 0x10000>;
 205                 interrupts = <0 37 4>;
 206                 gpio-controller;
 207                 little-endian;
 208                 #gpio-cells = <2>;
 209                 interrupt-controller;
 210                 #interrupt-cells = <2>;
 211         };
 212
 213         watchdog@23a0000 {
 214                 compatible = "arm,sbsa-gwdt";
 215                 reg = <0x0 0x23a0000 0 0x1000>,
 216                       <0x0 0x2390000 0 0x1000>;
 217                 timeout-sec = <30>;
 218         };
 219
 220         usb0: usb3@3100000 {
 221                 compatible = "fsl,layerscape-dwc3";
 222                 reg = <0x0 0x3100000 0x0 0x10000>;
 223                 interrupts = <0 80 0x4>; /* Level high type */
 224                 dr_mode = "host";
 225         };
 226
 227         usb1: usb3@3110000 {
 228                 compatible = "fsl,layerscape-dwc3";
 229                 reg = <0x0 0x3110000 0x0 0x10000>;
 230                 interrupts = <0 81 0x4>; /* Level high type */
 231                 dr_mode = "host";
 232         };
 233
 234         esdhc0: esdhc@2140000 {
 235                 compatible = "fsl,esdhc";
 236                 reg = <0x0 0x2140000 0x0 0x10000>;
 237                 interrupts = <0 28 0x4>; /* Level high type */
 238                 clocks = <&clockgen 4 1>;
 239                 voltage-ranges = <1800 1800 3300 3300>;
 240                 sdhci,auto-cmd12;
 241                 little-endian;
 242                 bus-width = <4>;
 243                 status = "disabled";
 244         };
 245
 246         esdhc1: esdhc@2150000 {
 247                 compatible = "fsl,esdhc";
 248                 reg = <0x0 0x2150000 0x0 0x10000>;
 249                 interrupts = <0 63 0x4>; /* Level high type */
 250                 clocks = <&clockgen 4 1>;
 251                 voltage-ranges = <1800 1800 3300 3300>;
 252                 sdhci,auto-cmd12;
 253                 non-removable;
 254                 little-endian;
 255                 bus-width = <4>;
 256                 status = "disabled";
 257         };
 258
 259         sata0: sata@3200000 {
 260                         compatible = "fsl,ls2080a-ahci";
 261                         reg = <0x0 0x3200000 0x0 0x10000>;
 262                         interrupts = <0 133 4>;
 263                         clocks = <&clockgen 4 3>;
 264                         status = "disabled";
 265
 266         };
 267
 268         sata1: sata@3210000 {
 269                         compatible = "fsl,ls2080a-ahci";
 270                         reg = <0x0 0x3210000 0x0 0x10000>;
 271                         interrupts = <0 136 4>;
 272                         clocks = <&clockgen 4 3>;
 273                         status = "disabled";
 274
 275         };
 276
 277         sata2: sata@3220000 {
 278                         compatible = "fsl,ls2080a-ahci";
 279                         reg = <0x0 0x3220000 0x0 0x10000>;
 280                         interrupts = <0 97 4>;
 281                         clocks = <&clockgen 4 3>;
 282                         status = "disabled";
 283
 284         };
 285
 286         sata3: sata@3230000 {
 287                         compatible = "fsl,ls2080a-ahci";
 288                         reg = <0x0 0x3230000 0x0 0x10000>;
 289                         interrupts = <0 100 4>;
 290                         clocks = <&clockgen 4 3>;
 291                         status = "disabled";
 292
 293         };
 294
 295         pcie@3400000 {
 296                 compatible = "fsl,lx2160a-pcie";
 297                 reg = <0x00 0x03400000 0x0 0x80000   /* PAB registers */
 298                        0x00 0x03480000 0x0 0x40000   /* LUT registers */
 299                        0x00 0x034c0000 0x0 0x40000   /* PF control registers */
 300                        0x80 0x00000000 0x0 0x2000>; /* configuration space */
 301                 reg-names = "ccsr", "lut", "pf_ctrl", "config";
 302                 #address-cells = <3>;
 303                 #size-cells = <2>;
 304                 device_type = "pci";
 305                 bus-range = <0x0 0xff>;
 306                 ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
 307         };
 308
 309         pcie@3500000 {
 310                 compatible = "fsl,lx2160a-pcie";
 311                 reg = <0x00 0x03500000 0x0 0x80000   /* PAB registers */
 312                        0x00 0x03580000 0x0 0x40000   /* LUT registers */
 313                        0x00 0x035c0000 0x0 0x40000   /* PF control registers */
 314                        0x88 0x00000000 0x0 0x2000>; /* configuration space */
 315                 reg-names = "ccsr", "lut", "pf_ctrl", "config";
 316                 #address-cells = <3>;
 317                 #size-cells = <2>;
 318                 device_type = "pci";
 319                 num-lanes = <2>;
 320                 bus-range = <0x0 0xff>;
 321                 ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>;
 322         };
 323
 324         pcie@3600000 {
 325                 compatible = "fsl,lx2160a-pcie";
 326                 reg = <0x00 0x03600000 0x0 0x80000   /* PAB registers */
 327                        0x00 0x03680000 0x0 0x40000   /* LUT registers */
 328                        0x00 0x036c0000 0x0 0x40000   /* PF control registers */
 329                        0x90 0x00000000 0x0 0x2000>; /* configuration space */
 330                 reg-names = "ccsr", "lut", "pf_ctrl", "config";
 331                 #address-cells = <3>;
 332                 #size-cells = <2>;
 333                 device_type = "pci";
 334                 bus-range = <0x0 0xff>;
 335                 ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>;
 336         };
 337
 338         pcie@3700000 {
 339                 compatible = "fsl,lx2160a-pcie";
 340                 reg = <0x00 0x03700000 0x0 0x80000   /* PAB registers */
 341                        0x00 0x03780000 0x0 0x40000   /* LUT registers */
 342                        0x00 0x037c0000 0x0 0x40000   /* PF control registers */
 343                        0x98 0x00000000 0x0 0x2000>; /* configuration space */
 344                 reg-names = "ccsr", "lut", "pf_ctrl", "config";
 345                 #address-cells = <3>;
 346                 #size-cells = <2>;
 347                 device_type = "pci";
 348                 bus-range = <0x0 0xff>;
 349                 ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>;
 350         };
 351
 352         pcie@3800000 {
 353                 compatible = "fsl,lx2160a-pcie";
 354                 reg = <0x00 0x03800000 0x0 0x80000   /* PAB registers */
 355                        0x00 0x03880000 0x0 0x40000   /* LUT registers */
 356                        0x00 0x038c0000 0x0 0x40000   /* PF control registers */
 357                        0xa0 0x00000000 0x0 0x2000>; /* configuration space */
 358                 reg-names = "ccsr", "lut", "pf_ctrl", "config";
 359                 #address-cells = <3>;
 360                 #size-cells = <2>;
 361                 device_type = "pci";
 362                 bus-range = <0x0 0xff>;
 363                 ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>;
 364         };
 365
 366         pcie@3900000 {
 367                 compatible = "fsl,lx2160a-pcie";
 368                 reg = <0x00 0x03900000 0x0 0x80000   /* PAB registers */
 369                        0x00 0x03980000 0x0 0x40000   /* LUT registers */
 370                        0x00 0x039c0000 0x0 0x40000   /* PF control registers */
 371                        0xa8 0x00000000 0x0 0x2000>; /* configuration space */
 372                 reg-names = "ccsr", "lut", "pf_ctrl", "config";
 373                 #address-cells = <3>;
 374                 #size-cells = <2>;
 375                 device_type = "pci";
 376                 bus-range = <0x0 0xff>;
 377                 ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>;
 378         };
 379
 380         fsl_mc: fsl-mc@80c000000 {
 381                 compatible = "fsl,qoriq-mc", "simple-mfd";
 382                 reg = <0x00000008 0x0c000000 0 0x40>,
 383                       <0x00000000 0x08340000 0 0x40000>;
 384                 #address-cells = <3>;
 385                 #size-cells = <1>;
 386
 387                 /*
 388                  * Region type 0x0 - MC portals
 389                  * Region type 0x1 - QBMAN portals
 390                  */
 391                 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
 392                           0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
 393
 394                 dpmacs {
 395                         compatible = "simple-mfd";
 396                         #address-cells = <1>;
 397                         #size-cells = <0>;
 398
 399                         dpmac1: dpmac@1 {
 400                                 compatible = "fsl,qoriq-mc-dpmac";
 401                                 reg = <0x1>;
 402                                 status = "disabled";
 403                         };
 404
 405                         dpmac2: dpmac@2 {
 406                                 compatible = "fsl,qoriq-mc-dpmac";
 407                                 reg = <0x2>;
 408                                 status = "disabled";
 409                         };
 410
 411                         dpmac3: dpmac@3 {
 412                                 compatible = "fsl,qoriq-mc-dpmac";
 413                                 reg = <0x3>;
 414                                 status = "disabled";
 415                         };
 416
 417                         dpmac4: dpmac@4 {
 418                                 compatible = "fsl,qoriq-mc-dpmac";
 419                                 reg = <0x4>;
 420                                 status = "disabled";
 421                         };
 422
 423                         dpmac5: dpmac@5 {
 424                                 compatible = "fsl,qoriq-mc-dpmac";
 425                                 reg = <0x5>;
 426                                 status = "disabled";
 427                         };
 428
 429                         dpmac6: dpmac@6 {
 430                                 compatible = "fsl,qoriq-mc-dpmac";
 431                                 reg = <0x6>;
 432                                 status = "disabled";
 433                         };
 434
 435                         dpmac7: dpmac@7 {
 436                                 compatible = "fsl,qoriq-mc-dpmac";
 437                                 reg = <0x7>;
 438                                 status = "disabled";
 439                         };
 440
 441                         dpmac8: dpmac@8 {
 442                                 compatible = "fsl,qoriq-mc-dpmac";
 443                                 reg = <0x8>;
 444                                 status = "disabled";
 445                         };
 446
 447                         dpmac9: dpmac@9 {
 448                                 compatible = "fsl,qoriq-mc-dpmac";
 449                                 reg = <0x9>;
 450                                 status = "disabled";
 451                         };
 452
 453                         dpmac10: dpmac@a {
 454                                 compatible = "fsl,qoriq-mc-dpmac";
 455                                 reg = <0xa>;
 456                                 status = "disabled";
 457                         };
 458
 459                         dpmac11: dpmac@b {
 460                                 compatible = "fsl,qoriq-mc-dpmac";
 461                                 reg = <0xb>;
 462                                 status = "disabled";
 463                         };
 464
 465                         dpmac12: dpmac@c {
 466                                 compatible = "fsl,qoriq-mc-dpmac";
 467                                 reg = <0xc>;
 468                                 status = "disabled";
 469                         };
 470
 471                         dpmac13: dpmac@d {
 472                                 compatible = "fsl,qoriq-mc-dpmac";
 473                                 reg = <0xd>;
 474                                 status = "disabled";
 475                         };
 476
 477                         dpmac14: dpmac@e {
 478                                 compatible = "fsl,qoriq-mc-dpmac";
 479                                 reg = <0xe>;
 480                                 status = "disabled";
 481                         };
 482
 483                         dpmac15: dpmac@f {
 484                                 compatible = "fsl,qoriq-mc-dpmac";
 485                                 reg = <0xf>;
 486                                 status = "disabled";
 487                         };
 488
 489                         dpmac16: dpmac@10 {
 490                                 compatible = "fsl,qoriq-mc-dpmac";
 491                                 reg = <0x10>;
 492                                 status = "disabled";
 493                         };
 494
 495                         dpmac17: dpmac@11 {
 496                                 compatible = "fsl,qoriq-mc-dpmac";
 497                                 reg = <0x11>;
 498                                 status = "disabled";
 499                         };
 500
 501                         dpmac18: dpmac@12 {
 502                                 compatible = "fsl,qoriq-mc-dpmac";
 503                                 reg = <0x12>;
 504                                 status = "disabled";
 505                         };
 506                 };
 507         };
 508
 509         /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
 510         emdio1: mdio@8b96000 {
 511                 compatible = "fsl,ls-mdio";
 512                 reg = <0x0 0x8b96000 0x0 0x1000>;
 513                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 514                 #address-cells = <1>;
 515                 #size-cells = <0>;
 516                 status = "disabled";
 517         };
 518
 519         /* WRIOP0: 0x8b8_0000, E-MDIO2: 0x1_7000 */
 520         emdio2: mdio@8b97000 {
 521                 compatible = "fsl,ls-mdio";
 522                 reg = <0x0 0x8b97000 0x0 0x1000>;
 523                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 524                 #address-cells = <1>;
 525                 #size-cells = <0>;
 526                 status = "disabled";
 527         };
 528         firmware {
 529                 optee {
 530                         compatible = "linaro,optee-tz";
 531                         method = "smc";
 532                 };
 533         };
 534 };