arch/arm/dts/fsl-lx2160a.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * NXP lx2160a SOC common device tree source
   4  *
   5  * Copyright 2018 NXP
   6  *
   7  */
   8
   9 / {
  10         compatible = "fsl,lx2160a";
  11         interrupt-parent = <&gic>;
  12         #address-cells = <2>;
  13         #size-cells = <2>;
  14
  15         memory@80000000 {
  16                 device_type = "memory";
  17                 reg = <0x00000000 0x80000000 0 0x80000000>;
  18                       /* DRAM space - 1, size : 2 GB DRAM */
  19         };
  20
  21         sysclk: sysclk {
  22                 compatible = "fixed-clock";
  23                 #clock-cells = <0>;
  24                 clock-frequency = <100000000>;
  25                 clock-output-names = "sysclk";
  26         };
  27
  28         clockgen: clocking@1300000 {
  29                 compatible = "fsl,ls2080a-clockgen";
  30                 reg = <0 0x1300000 0 0xa0000>;
  31                 #clock-cells = <2>;
  32                 clocks = <&sysclk>;
  33         };
  34
  35         gic: interrupt-controller@6000000 {
  36                 compatible = "arm,gic-v3";
  37                 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
  38                       <0x0 0x06200000 0 0x100000>; /* GICR */
  39                 #interrupt-cells = <3>;
  40                 interrupt-controller;
  41                 interrupts = <1 9 0x4>;
  42         };
  43
  44         timer {
  45                 compatible = "arm,armv8-timer";
  46                 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
  47                              <1 14 0x8>, /* Physical NS PPI, active-low */
  48                              <1 11 0x8>, /* Virtual PPI, active-low */
  49                              <1 10 0x8>; /* Hypervisor PPI, active-low */
  50         };
  51
  52         uart0: serial@21c0000 {
  53                 compatible = "arm,pl011";
  54                 reg = <0x0 0x21c0000 0x0 0x1000>;
  55                 clocks = <&clockgen 4 0>;
  56         };
  57
  58         uart1: serial@21d0000 {
  59                 compatible = "arm,pl011";
  60                 reg = <0x0 0x21d0000 0x0 0x1000>;
  61                 clocks = <&clockgen 4 0>;
  62         };
  63
  64         uart2: serial@21e0000 {
  65                 compatible = "arm,pl011";
  66                 reg = <0x0 0x21e0000 0x0 0x1000>;
  67                 clocks = <&clockgen 4 0>;
  68                 status = "disabled";
  69         };
  70
  71         uart3: serial@21f0000 {
  72                 compatible = "arm,pl011";
  73                 reg = <0x0 0x21f0000 0x0 0x1000>;
  74                 clocks = <&clockgen 4 0>;
  75                 status = "disabled";
  76         };
  77
  78         dspi0: dspi@2100000 {
  79                 compatible = "fsl,vf610-dspi";
  80                 #address-cells = <1>;
  81                 #size-cells = <0>;
  82                 reg = <0x0 0x2100000 0x0 0x10000>;
  83                 interrupts = <0 26 0x4>; /* Level high type */
  84                 num-cs = <6>;
  85         };
  86
  87         dspi1: dspi@2110000 {
  88                 compatible = "fsl,vf610-dspi";
  89                 #address-cells = <1>;
  90                 #size-cells = <0>;
  91                 reg = <0x0 0x2110000 0x0 0x10000>;
  92                 interrupts = <0 26 0x4>; /* Level high type */
  93                 num-cs = <6>;
  94         };
  95
  96         dspi2: dspi@2120000 {
  97                 compatible = "fsl,vf610-dspi";
  98                 #address-cells = <1>;
  99                 #size-cells = <0>;
 100                 reg = <0x0 0x2120000 0x0 0x10000>;
 101                 interrupts = <0 241 0x4>; /* Level high type */
 102                 num-cs = <6>;
 103         };
 104
 105         usb0: usb3@3100000 {
 106                 compatible = "fsl,layerscape-dwc3";
 107                 reg = <0x0 0x3100000 0x0 0x10000>;
 108                 interrupts = <0 80 0x4>; /* Level high type */
 109                 dr_mode = "host";
 110         };
 111
 112         usb1: usb3@3110000 {
 113                 compatible = "fsl,layerscape-dwc3";
 114                 reg = <0x0 0x3110000 0x0 0x10000>;
 115                 interrupts = <0 81 0x4>; /* Level high type */
 116                 dr_mode = "host";
 117         };
 118
 119         esdhc0: esdhc@2140000 {
 120                 compatible = "fsl,esdhc";
 121                 reg = <0x0 0x2140000 0x0 0x10000>;
 122                 interrupts = <0 28 0x4>; /* Level high type */
 123                 clocks = <&clockgen 4 1>;
 124                 voltage-ranges = <1800 1800 3300 3300>;
 125                 sdhci,auto-cmd12;
 126                 little-endian;
 127                 bus-width = <4>;
 128                 status = "disabled";
 129         };
 130
 131         esdhc1: esdhc@2150000 {
 132                 compatible = "fsl,esdhc";
 133                 reg = <0x0 0x2150000 0x0 0x10000>;
 134                 interrupts = <0 63 0x4>; /* Level high type */
 135                 clocks = <&clockgen 4 1>;
 136                 voltage-ranges = <1800 1800 3300 3300>;
 137                 sdhci,auto-cmd12;
 138                 non-removable;
 139                 little-endian;
 140                 bus-width = <4>;
 141                 status = "disabled";
 142         };
 143
 144         sata0: sata@3200000 {
 145                         compatible = "fsl,ls2080a-ahci";
 146                         reg = <0x0 0x3200000 0x0 0x10000>;
 147                         interrupts = <0 133 4>;
 148                         clocks = <&clockgen 4 3>;
 149                         status = "disabled";
 150
 151         };
 152
 153         sata1: sata@3210000 {
 154                         compatible = "fsl,ls2080a-ahci";
 155                         reg = <0x0 0x3210000 0x0 0x10000>;
 156                         interrupts = <0 136 4>;
 157                         clocks = <&clockgen 4 3>;
 158                         status = "disabled";
 159
 160         };
 161
 162         sata2: sata@3220000 {
 163                         compatible = "fsl,ls2080a-ahci";
 164                         reg = <0x0 0x3220000 0x0 0x10000>;
 165                         interrupts = <0 97 4>;
 166                         clocks = <&clockgen 4 3>;
 167                         status = "disabled";
 168
 169         };
 170
 171         sata3: sata@3230000 {
 172                         compatible = "fsl,ls2080a-ahci";
 173                         reg = <0x0 0x3230000 0x0 0x10000>;
 174                         interrupts = <0 100 4>;
 175                         clocks = <&clockgen 4 3>;
 176                         status = "disabled";
 177
 178         };
 179
 180         pcie@3400000 {
 181                 compatible = "fsl,lx2160a-pcie";
 182                 reg = <0x00 0x03400000 0x0 0x80000   /* PAB registers */
 183                        0x00 0x03480000 0x0 0x40000   /* LUT registers */
 184                        0x00 0x034c0000 0x0 0x40000   /* PF control registers */
 185                        0x80 0x00000000 0x0 0x1000>; /* configuration space */
 186                 reg-names = "ccsr", "lut", "pf_ctrl", "config";
 187                 #address-cells = <3>;
 188                 #size-cells = <2>;
 189                 device_type = "pci";
 190                 bus-range = <0x0 0xff>;
 191                 ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
 192         };
 193
 194         pcie@3500000 {
 195                 compatible = "fsl,lx2160a-pcie";
 196                 reg = <0x00 0x03500000 0x0 0x80000   /* PAB registers */
 197                        0x00 0x03580000 0x0 0x40000   /* LUT registers */
 198                        0x00 0x035c0000 0x0 0x40000   /* PF control registers */
 199                        0x88 0x00000000 0x0 0x1000>; /* configuration space */
 200                 reg-names = "ccsr", "lut", "pf_ctrl", "config";
 201                 #address-cells = <3>;
 202                 #size-cells = <2>;
 203                 device_type = "pci";
 204                 num-lanes = <2>;
 205                 bus-range = <0x0 0xff>;
 206                 ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>;
 207         };
 208
 209         pcie@3600000 {
 210                 compatible = "fsl,lx2160a-pcie";
 211                 reg = <0x00 0x03600000 0x0 0x80000   /* PAB registers */
 212                        0x00 0x03680000 0x0 0x40000   /* LUT registers */
 213                        0x00 0x036c0000 0x0 0x40000   /* PF control registers */
 214                        0x90 0x00000000 0x0 0x1000>; /* configuration space */
 215                 reg-names = "ccsr", "lut", "pf_ctrl", "config";
 216                 #address-cells = <3>;
 217                 #size-cells = <2>;
 218                 device_type = "pci";
 219                 bus-range = <0x0 0xff>;
 220                 ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>;
 221         };
 222
 223         pcie@3700000 {
 224                 compatible = "fsl,lx2160a-pcie";
 225                 reg = <0x00 0x03700000 0x0 0x80000   /* PAB registers */
 226                        0x00 0x03780000 0x0 0x40000   /* LUT registers */
 227                        0x00 0x037c0000 0x0 0x40000   /* PF control registers */
 228                        0x98 0x00000000 0x0 0x1000>; /* configuration space */
 229                 reg-names = "ccsr", "lut", "pf_ctrl", "config";
 230                 #address-cells = <3>;
 231                 #size-cells = <2>;
 232                 device_type = "pci";
 233                 bus-range = <0x0 0xff>;
 234                 ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>;
 235         };
 236
 237         pcie@3800000 {
 238                 compatible = "fsl,lx2160a-pcie";
 239                 reg = <0x00 0x03800000 0x0 0x80000   /* PAB registers */
 240                        0x00 0x03880000 0x0 0x40000   /* LUT registers */
 241                        0x00 0x038c0000 0x0 0x40000   /* PF control registers */
 242                        0xa0 0x00000000 0x0 0x1000>; /* configuration space */
 243                 reg-names = "ccsr", "lut", "pf_ctrl", "config";
 244                 #address-cells = <3>;
 245                 #size-cells = <2>;
 246                 device_type = "pci";
 247                 bus-range = <0x0 0xff>;
 248                 ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>;
 249         };
 250
 251         pcie@3900000 {
 252                 compatible = "fsl,lx2160a-pcie";
 253                 reg = <0x00 0x03900000 0x0 0x80000   /* PAB registers */
 254                        0x00 0x03980000 0x0 0x40000   /* LUT registers */
 255                        0x00 0x039c0000 0x0 0x40000   /* PF control registers */
 256                        0xa8 0x00000000 0x0 0x1000>; /* configuration space */
 257                 reg-names = "ccsr", "lut", "pf_ctrl", "config";
 258                 #address-cells = <3>;
 259                 #size-cells = <2>;
 260                 device_type = "pci";
 261                 bus-range = <0x0 0xff>;
 262                 ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>;
 263         };
 264 };