arch/arm/dts/fsl-lx2160a-rdb.dts

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * NXP LX2160ARDB device tree source
   4  *
   5  * Author:      Priyanka Jain <priyanka.jain@nxp.com>
   6  *              Sriram Dash <sriram.dash@nxp.com>
   7  *
   8  * Copyright 2018 NXP
   9  *
  10  */
  11
  12 /dts-v1/;
  13
  14 #include "fsl-lx2160a.dtsi"
  15
  16 / {
  17         model = "NXP Layerscape LX2160ARDB Board";
  18         compatible = "fsl,lx2160ardb", "fsl,lx2160a";
  19         aliases {
  20                 spi0 = &fspi;
  21         };
  22 };
  23
  24 &dpmac3 {
  25         status = "okay";
  26         phy-handle = <&aquantia_phy1>;
  27         phy-connection-type = "usxgmii";
  28 };
  29
  30 &dpmac4 {
  31         status = "okay";
  32         phy-handle = <&aquantia_phy2>;
  33         phy-connection-type = "usxgmii";
  34 };
  35
  36 &dpmac17 {
  37         status = "okay";
  38         phy-handle = <&rgmii_phy1>;
  39         phy-connection-type = "rgmii-id";
  40 };
  41
  42 &dpmac18 {
  43         status = "okay";
  44         phy-handle = <&rgmii_phy2>;
  45         phy-connection-type = "rgmii-id";
  46 };
  47
  48 &emdio1 {
  49         status = "okay";
  50         rgmii_phy1: ethernet-phy@1 {
  51                 /* AR8035 PHY - "compatible" property not strictly needed */
  52                 compatible = "ethernet-phy-id004d.d072";
  53                 reg = <0x1>;
  54                 /* Poll mode - no "interrupts" property defined */
  55         };
  56         rgmii_phy2: ethernet-phy@2 {
  57                 /* AR8035 PHY - "compatible" property not strictly needed */
  58                 compatible = "ethernet-phy-id004d.d072";
  59                 reg = <0x2>;
  60                 /* Poll mode - no "interrupts" property defined */
  61         };
  62         aquantia_phy1: ethernet-phy@4 {
  63                 /* AQR107 PHY - "compatible" property not strictly needed */
  64                 compatible = "ethernet-phy-ieee802.3-c45";
  65                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
  66                 reg = <0x4>;
  67         };
  68         aquantia_phy2: ethernet-phy@5 {
  69                 /* AQR107 PHY - "compatible" property not strictly needed */
  70                 compatible = "ethernet-phy-ieee802.3-c45";
  71                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  72                 reg = <0x5>;
  73         };
  74 };
  75
  76 &esdhc0 {
  77         status = "okay";
  78 };
  79
  80 &esdhc1 {
  81         status = "okay";
  82         mmc-hs200-1_8v;
  83         mmc-hs400-1_8v;
  84         bus-width = <8>;
  85 };
  86
  87 &fspi {
  88         status = "okay";
  89
  90         mt35xu512aba0: flash@0 {
  91                 #address-cells = <1>;
  92                 #size-cells = <1>;
  93                 compatible = "jedec,spi-nor";
  94                 spi-max-frequency = <50000000>;
  95                 reg = <0>;
  96                 spi-rx-bus-width = <8>;
  97                 spi-tx-bus-width = <1>;
  98         };
  99
 100         mt35xu512aba1: flash@1 {
 101                 #address-cells = <1>;
 102                 #size-cells = <1>;
 103                 compatible = "jedec,spi-nor";
 104                 spi-max-frequency = <50000000>;
 105                 reg = <1>;
 106                 spi-rx-bus-width = <8>;
 107                 spi-tx-bus-width = <1>;
 108         };
 109 };
 110
 111 &i2c0 {
 112         status = "okay";
 113         u-boot,dm-pre-reloc;
 114 };
 115
 116 &i2c4 {
 117         status = "okay";
 118
 119         rtc@51 {
 120                 compatible = "pcf2127-rtc";
 121                 reg = <0x51>;
 122         };
 123 };
 124
 125 &sata0 {
 126         status = "okay";
 127 };
 128
 129 &sata1 {
 130         status = "okay";
 131 };
 132
 133 &sata2 {
 134         status = "okay";
 135 };
 136
 137 &sata3 {
 138         status = "okay";
 139 };