1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * NXP LX2160AQDS common device tree source
5 * Copyright 2018-2020 NXP
9 #include "fsl-lx2160a.dtsi"
19 phy-handle = <&rgmii_phy1>;
20 phy-connection-type = "rgmii-id";
25 phy-handle = <&rgmii_phy2>;
26 phy-connection-type = "rgmii-id";
36 compatible = "spi-flash";
37 spi-max-frequency = <3000000>;
42 dflash1: sst25wf040b {
45 compatible = "spi-flash";
46 spi-max-frequency = <3000000>;
54 compatible = "spi-flash";
55 spi-max-frequency = <3000000>;
69 compatible = "spi-flash";
70 spi-max-frequency = <3000000>;
75 dflash4: sst25wf040b {
78 compatible = "spi-flash";
79 spi-max-frequency = <3000000>;
87 compatible = "spi-flash";
88 spi-max-frequency = <3000000>;
100 #address-cells = <1>;
102 compatible = "spi-flash";
103 spi-max-frequency = <3000000>;
108 dflash7: sst25wf040b {
109 #address-cells = <1>;
111 compatible = "spi-flash";
112 spi-max-frequency = <3000000>;
118 #address-cells = <1>;
120 compatible = "spi-flash";
121 spi-max-frequency = <3000000>;
149 #address-cells = <1>;
151 compatible = "simple-mfd";
155 #address-cells = <1>;
157 compatible = "mdio-mux-i2creg";
159 #mux-control-cells = <1>;
160 mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3
161 mdio-parent-bus = <&emdio1>;
164 #address-cells = <1>;
168 rgmii_phy1: ethernet-phy@1 {
173 #address-cells = <1>;
177 rgmii_phy2: ethernet-phy@2 {
182 emdio1_slot1: mdio@c0 { /* I/O Slot #1 */
184 device-name = "emdio1_slot1";
185 #address-cells = <1>;
189 emdio1_slot2: mdio@c8 { /* I/O Slot #2 */
191 device-name = "emdio1_slot2";
192 #address-cells = <1>;
196 emdio1_slot3: mdio@d0 { /* I/O Slot #3 */
198 device-name = "emdio1_slot3";
199 #address-cells = <1>;
203 emdio1_slot4: mdio@d8 { /* I/O Slot #4 */
205 device-name = "emdio1_slot4";
206 #address-cells = <1>;
210 emdio1_slot5: mdio@e0 { /* I/O Slot #5 */
212 device-name = "emdio1_slot5";
213 #address-cells = <1>;
217 emdio1_slot6: mdio@e8 { /* I/O Slot #6 */
219 device-name = "emdio1_slot6";
220 #address-cells = <1>;
224 emdio1_slot7: mdio@f0 { /* I/O Slot #7 */
226 device-name = "emdio1_slot7";
227 #address-cells = <1>;
231 emdio1_slot8: mdio@f8 { /* I/O Slot #8 */
233 device-name = "emdio1_slot8";
234 #address-cells = <1>;
242 compatible = "nxp,pca9547";
244 #address-cells = <1>;
248 #address-cells = <1>;
253 compatible = "pcf2127-rtc";
263 mt35xu512aba0: flash@0 {
264 #address-cells = <1>;
266 compatible = "jedec,spi-nor";
267 spi-max-frequency = <50000000>;
269 spi-rx-bus-width = <8>;
270 spi-tx-bus-width = <1>;