arch/arm/dts/fsl-lx2160a-qds.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * NXP LX2160AQDS common device tree source
   4  *
   5  * Copyright 2018-2019 NXP
   6  *
   7  */
   8
   9 #include "fsl-lx2160a.dtsi"
  10
  11 &dpmac17 {
  12         status = "okay";
  13         phy-handle = <&rgmii_phy1>;
  14         phy-connection-type = "rgmii-id";
  15 };
  16
  17 &dpmac18 {
  18         status = "okay";
  19         phy-handle = <&rgmii_phy2>;
  20         phy-connection-type = "rgmii-id";
  21 };
  22
  23 &dspi0 {
  24         bus-num = <0>;
  25         status = "okay";
  26
  27         dflash0: n25q128a {
  28                 #address-cells = <1>;
  29                 #size-cells = <1>;
  30                 compatible = "spi-flash";
  31                 spi-max-frequency = <3000000>;
  32                 spi-cpol;
  33                 spi-cpha;
  34                 reg = <0>;
  35         };
  36         dflash1: sst25wf040b {
  37                 #address-cells = <1>;
  38                 #size-cells = <1>;
  39                 compatible = "spi-flash";
  40                 spi-max-frequency = <3000000>;
  41                 spi-cpol;
  42                 spi-cpha;
  43                 reg = <1>;
  44         };
  45         dflash2: en25s64 {
  46                 #address-cells = <1>;
  47                 #size-cells = <1>;
  48                 compatible = "spi-flash";
  49                 spi-max-frequency = <3000000>;
  50                 spi-cpol;
  51                 spi-cpha;
  52                 reg = <2>;
  53         };
  54 };
  55
  56 &dspi1 {
  57         bus-num = <0>;
  58         status = "okay";
  59
  60         dflash3: n25q128a {
  61                 #address-cells = <1>;
  62                 #size-cells = <1>;
  63                 compatible = "spi-flash";
  64                 spi-max-frequency = <3000000>;
  65                 spi-cpol;
  66                 spi-cpha;
  67                 reg = <0>;
  68         };
  69         dflash4: sst25wf040b {
  70                 #address-cells = <1>;
  71                 #size-cells = <1>;
  72                 compatible = "spi-flash";
  73                 spi-max-frequency = <3000000>;
  74                 spi-cpol;
  75                 spi-cpha;
  76                 reg = <1>;
  77         };
  78         dflash5: en25s64 {
  79                 #address-cells = <1>;
  80                 #size-cells = <1>;
  81                 compatible = "spi-flash";
  82                 spi-max-frequency = <3000000>;
  83                 spi-cpol;
  84                 spi-cpha;
  85                 reg = <2>;
  86         };
  87 };
  88
  89 &dspi2 {
  90         bus-num = <0>;
  91         status = "okay";
  92
  93         dflash6: n25q128a {
  94                 #address-cells = <1>;
  95                 #size-cells = <1>;
  96                 compatible = "spi-flash";
  97                 spi-max-frequency = <3000000>;
  98                 spi-cpol;
  99                 spi-cpha;
 100                 reg = <0>;
 101         };
 102         dflash7: sst25wf040b {
 103                 #address-cells = <1>;
 104                 #size-cells = <1>;
 105                 compatible = "spi-flash";
 106                 spi-max-frequency = <3000000>;
 107                 spi-cpol;
 108                 spi-cpha;
 109                 reg = <1>;
 110         };
 111         dflash8: en25s64 {
 112                 #address-cells = <1>;
 113                 #size-cells = <1>;
 114                 compatible = "spi-flash";
 115                 spi-max-frequency = <3000000>;
 116                 spi-cpol;
 117                 spi-cpha;
 118                 reg = <2>;
 119         };
 120 };
 121
 122 &emdio1 {
 123         status = "okay";
 124 };
 125
 126 &emdio2 {
 127         status = "okay";
 128 };
 129
 130 &esdhc0 {
 131         status = "okay";
 132 };
 133
 134 &esdhc1 {
 135         status = "okay";
 136 };
 137
 138 &i2c0 {
 139         status = "okay";
 140         u-boot,dm-pre-reloc;
 141
 142         fpga@66 {
 143                 #address-cells = <1>;
 144                 #size-cells = <0>;
 145                 compatible = "simple-mfd";
 146                 reg = <0x66>;
 147
 148                 mux-mdio@54 {
 149                         #address-cells = <1>;
 150                         #size-cells = <0>;
 151                         compatible = "mdio-mux-i2creg";
 152                         reg = <0x54>;
 153                         #mux-control-cells = <1>;
 154                         mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3
 155                         mdio-parent-bus = <&emdio1>;
 156
 157                         mdio@00 {
 158                                 #address-cells = <1>;
 159                                 #size-cells = <0>;
 160                                 reg = <0x00>;
 161
 162                                 rgmii_phy1: ethernet-phy@1 {
 163                                         reg = <0x1>;
 164                                 };
 165                         };
 166                         mdio@08 {
 167                                 #address-cells = <1>;
 168                                 #size-cells = <0>;
 169                                 reg = <0x40>;
 170
 171                                 rgmii_phy2: ethernet-phy@2 {
 172                                         reg = <0x2>;
 173                                 };
 174                         };
 175
 176                         emdio1_slot1: mdio@c0 { /* I/O Slot #1 */
 177                                 reg = <0xC0>;
 178                                 device-name = "emdio1_slot1";
 179                                 #address-cells = <1>;
 180                                 #size-cells = <0>;
 181                         };
 182
 183                         emdio1_slot2: mdio@c8 { /* I/O Slot #2 */
 184                                 reg = <0xC8>;
 185                                 device-name = "emdio1_slot2";
 186                                 #address-cells = <1>;
 187                                 #size-cells = <0>;
 188                         };
 189
 190                         emdio1_slot3: mdio@d0 { /* I/O Slot #3 */
 191                                 reg = <0xD0>;
 192                                 device-name = "emdio1_slot3";
 193                                 #address-cells = <1>;
 194                                 #size-cells = <0>;
 195                         };
 196
 197                         emdio1_slot4: mdio@d8 { /* I/O Slot #4 */
 198                                 reg = <0xD8>;
 199                                 device-name = "emdio1_slot4";
 200                                 #address-cells = <1>;
 201                                 #size-cells = <0>;
 202                         };
 203
 204                         emdio1_slot5: mdio@e0 { /* I/O Slot #5 */
 205                                 reg = <0xE0>;
 206                                 device-name = "emdio1_slot5";
 207                                 #address-cells = <1>;
 208                                 #size-cells = <0>;
 209                         };
 210
 211                         emdio1_slot6: mdio@e8 { /* I/O Slot #6 */
 212                                 reg = <0xE8>;
 213                                 device-name = "emdio1_slot6";
 214                                 #address-cells = <1>;
 215                                 #size-cells = <0>;
 216                         };
 217
 218                         emdio1_slot7: mdio@f0 { /* I/O Slot #7 */
 219                                 reg = <0xF0>;
 220                                 device-name = "emdio1_slot7";
 221                                 #address-cells = <1>;
 222                                 #size-cells = <0>;
 223                         };
 224
 225                         emdio1_slot8: mdio@f8 { /* I/O Slot #8 */
 226                                 reg = <0xF8>;
 227                                 device-name = "emdio1_slot8";
 228                                 #address-cells = <1>;
 229                                 #size-cells = <0>;
 230                         };
 231                 };
 232
 233         };
 234
 235         i2c-mux@77 {
 236                 compatible = "nxp,pca9547";
 237                 reg = <0x77>;
 238                 #address-cells = <1>;
 239                 #size-cells = <0>;
 240
 241                 i2c@3 {
 242                         #address-cells = <1>;
 243                         #size-cells = <0>;
 244                         reg = <0x3>;
 245
 246                         rtc@51 {
 247                                 compatible = "pcf2127-rtc";
 248                                 reg = <0x51>;
 249                         };
 250                 };
 251         };
 252 };
 253
 254 &sata0 {
 255         status = "okay";
 256 };
 257
 258 &sata1 {
 259         status = "okay";
 260 };
 261
 262 &sata2 {
 263         status = "okay";
 264 };
 265
 266 &sata3 {
 267         status = "okay";
 268 };