arch/arm/dts/fsl-lx2160a-qds.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * NXP LX2160AQDS common device tree source
   4  *
   5  * Copyright 2018-2020 NXP
   6  *
   7  */
   8
   9 #include "fsl-lx2160a.dtsi"
  10
  11 / {
  12         aliases {
  13                 spi0 = &fspi;
  14         };
  15 };
  16
  17 &dpmac17 {
  18         status = "okay";
  19         phy-handle = <&rgmii_phy1>;
  20         phy-connection-type = "rgmii-id";
  21 };
  22
  23 &dpmac18 {
  24         status = "okay";
  25         phy-handle = <&rgmii_phy2>;
  26         phy-connection-type = "rgmii-id";
  27 };
  28
  29 &dspi0 {
  30         bus-num = <0>;
  31         status = "okay";
  32
  33         dflash0: n25q128a {
  34                 #address-cells = <1>;
  35                 #size-cells = <1>;
  36                 compatible = "spi-flash";
  37                 spi-max-frequency = <3000000>;
  38                 spi-cpol;
  39                 spi-cpha;
  40                 reg = <0>;
  41         };
  42         dflash1: sst25wf040b {
  43                 #address-cells = <1>;
  44                 #size-cells = <1>;
  45                 compatible = "spi-flash";
  46                 spi-max-frequency = <3000000>;
  47                 spi-cpol;
  48                 spi-cpha;
  49                 reg = <1>;
  50         };
  51         dflash2: en25s64 {
  52                 #address-cells = <1>;
  53                 #size-cells = <1>;
  54                 compatible = "spi-flash";
  55                 spi-max-frequency = <3000000>;
  56                 spi-cpol;
  57                 spi-cpha;
  58                 reg = <2>;
  59         };
  60 };
  61
  62 &dspi1 {
  63         bus-num = <0>;
  64         status = "okay";
  65
  66         dflash3: n25q128a {
  67                 #address-cells = <1>;
  68                 #size-cells = <1>;
  69                 compatible = "spi-flash";
  70                 spi-max-frequency = <3000000>;
  71                 spi-cpol;
  72                 spi-cpha;
  73                 reg = <0>;
  74         };
  75         dflash4: sst25wf040b {
  76                 #address-cells = <1>;
  77                 #size-cells = <1>;
  78                 compatible = "spi-flash";
  79                 spi-max-frequency = <3000000>;
  80                 spi-cpol;
  81                 spi-cpha;
  82                 reg = <1>;
  83         };
  84         dflash5: en25s64 {
  85                 #address-cells = <1>;
  86                 #size-cells = <1>;
  87                 compatible = "spi-flash";
  88                 spi-max-frequency = <3000000>;
  89                 spi-cpol;
  90                 spi-cpha;
  91                 reg = <2>;
  92         };
  93 };
  94
  95 &dspi2 {
  96         bus-num = <0>;
  97         status = "okay";
  98
  99         dflash6: n25q128a {
 100                 #address-cells = <1>;
 101                 #size-cells = <1>;
 102                 compatible = "spi-flash";
 103                 spi-max-frequency = <3000000>;
 104                 spi-cpol;
 105                 spi-cpha;
 106                 reg = <0>;
 107         };
 108         dflash7: sst25wf040b {
 109                 #address-cells = <1>;
 110                 #size-cells = <1>;
 111                 compatible = "spi-flash";
 112                 spi-max-frequency = <3000000>;
 113                 spi-cpol;
 114                 spi-cpha;
 115                 reg = <1>;
 116         };
 117         dflash8: en25s64 {
 118                 #address-cells = <1>;
 119                 #size-cells = <1>;
 120                 compatible = "spi-flash";
 121                 spi-max-frequency = <3000000>;
 122                 spi-cpol;
 123                 spi-cpha;
 124                 reg = <2>;
 125         };
 126 };
 127
 128 &emdio1 {
 129         status = "okay";
 130 };
 131
 132 &emdio2 {
 133         status = "okay";
 134 };
 135
 136 &esdhc0 {
 137         status = "okay";
 138 };
 139
 140 &esdhc1 {
 141         status = "okay";
 142 };
 143
 144 &i2c0 {
 145         status = "okay";
 146         u-boot,dm-pre-reloc;
 147
 148         fpga@66 {
 149                 #address-cells = <1>;
 150                 #size-cells = <0>;
 151                 compatible = "simple-mfd";
 152                 reg = <0x66>;
 153
 154                 mux-mdio@54 {
 155                         #address-cells = <1>;
 156                         #size-cells = <0>;
 157                         compatible = "mdio-mux-i2creg";
 158                         reg = <0x54>;
 159                         #mux-control-cells = <1>;
 160                         mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3
 161                         mdio-parent-bus = <&emdio1>;
 162
 163                         mdio@00 {
 164                                 #address-cells = <1>;
 165                                 #size-cells = <0>;
 166                                 reg = <0x00>;
 167
 168                                 rgmii_phy1: ethernet-phy@1 {
 169                                         reg = <0x1>;
 170                                 };
 171                         };
 172                         mdio@08 {
 173                                 #address-cells = <1>;
 174                                 #size-cells = <0>;
 175                                 reg = <0x40>;
 176
 177                                 rgmii_phy2: ethernet-phy@2 {
 178                                         reg = <0x2>;
 179                                 };
 180                         };
 181
 182                         emdio1_slot1: mdio@c0 { /* I/O Slot #1 */
 183                                 reg = <0xC0>;
 184                                 device-name = "emdio1_slot1";
 185                                 #address-cells = <1>;
 186                                 #size-cells = <0>;
 187                         };
 188
 189                         emdio1_slot2: mdio@c8 { /* I/O Slot #2 */
 190                                 reg = <0xC8>;
 191                                 device-name = "emdio1_slot2";
 192                                 #address-cells = <1>;
 193                                 #size-cells = <0>;
 194                         };
 195
 196                         emdio1_slot3: mdio@d0 { /* I/O Slot #3 */
 197                                 reg = <0xD0>;
 198                                 device-name = "emdio1_slot3";
 199                                 #address-cells = <1>;
 200                                 #size-cells = <0>;
 201                         };
 202
 203                         emdio1_slot4: mdio@d8 { /* I/O Slot #4 */
 204                                 reg = <0xD8>;
 205                                 device-name = "emdio1_slot4";
 206                                 #address-cells = <1>;
 207                                 #size-cells = <0>;
 208                         };
 209
 210                         emdio1_slot5: mdio@e0 { /* I/O Slot #5 */
 211                                 reg = <0xE0>;
 212                                 device-name = "emdio1_slot5";
 213                                 #address-cells = <1>;
 214                                 #size-cells = <0>;
 215                         };
 216
 217                         emdio1_slot6: mdio@e8 { /* I/O Slot #6 */
 218                                 reg = <0xE8>;
 219                                 device-name = "emdio1_slot6";
 220                                 #address-cells = <1>;
 221                                 #size-cells = <0>;
 222                         };
 223
 224                         emdio1_slot7: mdio@f0 { /* I/O Slot #7 */
 225                                 reg = <0xF0>;
 226                                 device-name = "emdio1_slot7";
 227                                 #address-cells = <1>;
 228                                 #size-cells = <0>;
 229                         };
 230
 231                         emdio1_slot8: mdio@f8 { /* I/O Slot #8 */
 232                                 reg = <0xF8>;
 233                                 device-name = "emdio1_slot8";
 234                                 #address-cells = <1>;
 235                                 #size-cells = <0>;
 236                         };
 237                 };
 238
 239         };
 240
 241         i2c-mux@77 {
 242                 compatible = "nxp,pca9547";
 243                 reg = <0x77>;
 244                 #address-cells = <1>;
 245                 #size-cells = <0>;
 246
 247                 i2c@3 {
 248                         #address-cells = <1>;
 249                         #size-cells = <0>;
 250                         reg = <0x3>;
 251
 252                         rtc@51 {
 253                                 compatible = "pcf2127-rtc";
 254                                 reg = <0x51>;
 255                         };
 256                 };
 257         };
 258 };
 259
 260 &fspi {
 261         status = "okay";
 262
 263         mt35xu512aba0: flash@0 {
 264                 #address-cells = <1>;
 265                 #size-cells = <1>;
 266                 compatible = "jedec,spi-nor";
 267                 spi-max-frequency = <50000000>;
 268                 reg = <0>;
 269                 spi-rx-bus-width = <8>;
 270                 spi-tx-bus-width = <1>;
 271         };
 272 };
 273
 274 &sata0 {
 275         status = "okay";
 276 };
 277
 278 &sata1 {
 279         status = "okay";
 280 };
 281
 282 &sata2 {
 283         status = "okay";
 284 };
 285
 286 &sata3 {
 287         status = "okay";
 288 };