arch/arm/dts/fsl-ls2088a-rdb-qspi.dts

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * NXP ls2080a RDB board device tree source for QSPI-boot
   4  *
   5  * Author: Priyanka Jain <priyanka.jain@nxp.com>
   6  *
   7  * Copyright 2017 NXP
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "fsl-ls2080a.dtsi"
  13
  14 / {
  15         model = "Freescale Layerscape 2080a RDB Board";
  16         compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
  17
  18         aliases {
  19                 spi0 = &qspi;
  20                 spi1 = &dspi;
  21         };
  22 };
  23
  24 &dpmac1 {
  25         status = "okay";
  26         phy-handle = <&mdio1_phy1>;
  27         phy-connection-type = "xfi";
  28 };
  29
  30 &dpmac2 {
  31         status = "okay";
  32         phy-handle = <&mdio1_phy2>;
  33         phy-connection-type = "xfi";
  34 };
  35
  36 &dpmac3 {
  37         status = "okay";
  38         phy-handle = <&mdio1_phy3>;
  39         phy-connection-type = "xfi";
  40 };
  41
  42 &dpmac4 {
  43         status = "okay";
  44         phy-handle = <&mdio1_phy4>;
  45         phy-connection-type = "xfi";
  46 };
  47
  48 &dpmac5 {
  49         status = "okay";
  50         phy-handle = <&mdio2_phy1>;
  51         phy-connection-type = "xfi";
  52 };
  53
  54 &dpmac6 {
  55         status = "okay";
  56         phy-handle = <&mdio2_phy2>;
  57         phy-connection-type = "xfi";
  58 };
  59
  60 &dpmac7 {
  61         status = "okay";
  62         phy-handle = <&mdio2_phy3>;
  63         phy-connection-type = "xfi";
  64 };
  65
  66 &dpmac8 {
  67         status = "okay";
  68         phy-handle = <&mdio2_phy4>;
  69         phy-connection-type = "xfi";
  70 };
  71
  72 &emdio1 {
  73         status = "okay";
  74
  75         /* CS4340 PHYs */
  76         mdio1_phy1: emdio1_phy@1 {
  77                 reg = <0x10>;
  78         };
  79         mdio1_phy2: emdio1_phy@2 {
  80                 reg = <0x11>;
  81         };
  82         mdio1_phy3: emdio1_phy@3 {
  83                 reg = <0x12>;
  84         };
  85         mdio1_phy4: emdio1_phy@4 {
  86                 reg = <0x13>;
  87         };
  88 };
  89
  90 &emdio2 {
  91         status = "okay";
  92
  93         /* AQR405 PHYs */
  94         mdio2_phy1: emdio2_phy@1 {
  95                 compatible = "ethernet-phy-ieee802.3-c45";
  96                 reg = <0x0>;
  97         };
  98         mdio2_phy2: emdio2_phy@2 {
  99                 compatible = "ethernet-phy-ieee802.3-c45";
 100                 reg = <0x1>;
 101         };
 102         mdio2_phy3: emdio2_phy@3 {
 103                 compatible = "ethernet-phy-ieee802.3-c45";
 104                 reg = <0x2>;
 105         };
 106         mdio2_phy4: emdio2_phy@4 {
 107                 compatible = "ethernet-phy-ieee802.3-c45";
 108                 reg = <0x3>;
 109         };
 110 };
 111
 112 &dspi {
 113         bus-num = <0>;
 114         status = "okay";
 115
 116         dflash0: n25q512a {
 117                 #address-cells = <1>;
 118                 #size-cells = <1>;
 119                 compatible = "jedec,spi-nor";
 120                 spi-max-frequency = <3000000>;
 121                 spi-cpol;
 122                 spi-cpha;
 123                 reg = <0>;
 124         };
 125 };
 126
 127 &qspi {
 128         bus-num = <0>;
 129         status = "okay";
 130
 131         qflash0: s25fs512s@0 {
 132                 #address-cells = <1>;
 133                 #size-cells = <1>;
 134                 compatible = "jedec,spi-nor";
 135                 spi-max-frequency = <50000000>;
 136                 reg = <0>;
 137         };
 138
 139         qflash1: s25fs512s@1 {
 140                 #address-cells = <1>;
 141                 #size-cells = <1>;
 142                 compatible = "jedec,spi-nor";
 143                 spi-max-frequency = <50000000>;
 144                 reg = <1>;
 145         };
 146 };
 147
 148 &i2c0 {
 149         status = "okay";
 150         u-boot,dm-pre-reloc;
 151
 152         pca9547@75 {
 153                 compatible = "nxp,pca9547";
 154                 reg = <0x75>;
 155                 #address-cells = <1>;
 156                 #size-cells = <0>;
 157
 158                  i2c@1 {
 159                         #address-cells = <1>;
 160                         #size-cells = <0>;
 161                         reg = <0x01>;
 162                         rtc@68 {
 163                                 compatible = "dallas,ds3232";
 164                                 reg = <0x68>;
 165                         };
 166                 };
 167         };
 168 };
 169
 170 &sata {
 171         status = "okay";
 172 };