arch/arm/dts/fsl-ls2080a.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * Freescale ls2080a SOC common device tree source
   4  *
   5  * Copyright 2013-2015 Freescale Semiconductor, Inc.
   6  */
   7
   8 / {
   9         compatible = "fsl,ls2080a";
  10         interrupt-parent = <&gic>;
  11         #address-cells = <2>;
  12         #size-cells = <2>;
  13
  14         memory@80000000 {
  15                 device_type = "memory";
  16                 reg = <0x00000000 0x80000000 0 0x80000000>;
  17                       /* DRAM space - 1, size : 2 GB DRAM */
  18         };
  19
  20         gic: interrupt-controller@6000000 {
  21                 compatible = "arm,gic-v3";
  22                 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
  23                       <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
  24                 #interrupt-cells = <3>;
  25                 interrupt-controller;
  26                 interrupts = <1 9 0x4>;
  27         };
  28
  29         timer {
  30                 compatible = "arm,armv8-timer";
  31                 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
  32                              <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
  33                              <1 11 0x8>, /* Virtual PPI, active-low */
  34                              <1 10 0x8>; /* Hypervisor PPI, active-low */
  35         };
  36
  37         serial0: serial@21c0500 {
  38                 device_type = "serial";
  39                 compatible = "fsl,ns16550", "ns16550a";
  40                 reg = <0x0 0x21c0500 0x0 0x100>;
  41                 clock-frequency = <0>;  /* Updated by bootloader */
  42                 interrupts = <0 32 0x1>; /* edge triggered */
  43         };
  44
  45         serial1: serial@21c0600 {
  46                 device_type = "serial";
  47                 compatible = "fsl,ns16550", "ns16550a";
  48                 reg = <0x0 0x21c0600 0x0 0x100>;
  49                 clock-frequency = <0>;  /* Updated by bootloader */
  50                 interrupts = <0 32 0x1>; /* edge triggered */
  51         };
  52
  53         i2c0: i2c@2000000 {
  54                 status = "disabled";
  55                 compatible = "fsl,vf610-i2c";
  56                 #address-cells = <1>;
  57                 #size-cells = <0>;
  58                 reg = <0x0 0x2000000 0x0 0x10000>;
  59                 interrupts = <0 34 0x4>; /* Level high type */
  60         };
  61
  62         i2c1: i2c@2010000 {
  63                 status = "disabled";
  64                 compatible = "fsl,vf610-i2c";
  65                 #address-cells = <1>;
  66                 #size-cells = <0>;
  67                 reg = <0x0 0x2010000 0x0 0x10000>;
  68                 interrupts = <0 34 0x4>; /* Level high type */
  69         };
  70
  71         i2c2: i2c@2020000 {
  72                 status = "disabled";
  73                 compatible = "fsl,vf610-i2c";
  74                 #address-cells = <1>;
  75                 #size-cells = <0>;
  76                 reg = <0x0 0x2020000 0x0 0x10000>;
  77                 interrupts = <0 35 0x4>; /* Level high type */
  78         };
  79
  80         i2c3: i2c@2030000 {
  81                 status = "disabled";
  82                 compatible = "fsl,vf610-i2c";
  83                 #address-cells = <1>;
  84                 #size-cells = <0>;
  85                 reg = <0x0 0x2030000 0x0 0x10000>;
  86                 interrupts = <0 35 0x4>; /* Level high type */
  87         };
  88
  89         dspi: dspi@2100000 {
  90                 compatible = "fsl,vf610-dspi";
  91                 #address-cells = <1>;
  92                 #size-cells = <0>;
  93                 reg = <0x0 0x2100000 0x0 0x10000>;
  94                 interrupts = <0 26 0x4>; /* Level high type */
  95                 num-cs = <6>;
  96         };
  97
  98         qspi: quadspi@1550000 {
  99                 compatible = "fsl,ls2080a-qspi";
 100                 #address-cells = <1>;
 101                 #size-cells = <0>;
 102                 reg = <0x0 0x20c0000 0x0 0x10000>,
 103                         <0x0 0x20000000 0x0 0x10000000>;
 104                 reg-names = "QuadSPI", "QuadSPI-memory";
 105                 status = "disabled";
 106         };
 107
 108         esdhc: esdhc@0 {
 109                 compatible = "fsl,esdhc";
 110                 reg = <0x0 0x2140000 0x0 0x10000>;
 111                 interrupts = <0 28 0x4>; /* Level high type */
 112                 little-endian;
 113                 bus-width = <4>;
 114         };
 115
 116         usb0: usb3@3100000 {
 117                 compatible = "fsl,layerscape-dwc3";
 118                 reg = <0x0 0x3100000 0x0 0x10000>;
 119                 interrupts = <0 80 0x4>; /* Level high type */
 120                 dr_mode = "host";
 121         };
 122
 123         usb1: usb3@3110000 {
 124                 compatible = "fsl,layerscape-dwc3";
 125                 reg = <0x0 0x3110000 0x0 0x10000>;
 126                 interrupts = <0 81 0x4>; /* Level high type */
 127                 dr_mode = "host";
 128         };
 129
 130         pcie@3400000 {
 131                 compatible = "fsl,ls-pcie", "snps,dw-pcie";
 132                 reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
 133                        0x00 0x03480000 0x0 0x80000   /* lut registers */
 134                        0x10 0x00000000 0x0 0x20000>; /* configuration space */
 135                 reg-names = "dbi", "lut", "config";
 136                 #address-cells = <3>;
 137                 #size-cells = <2>;
 138                 device_type = "pci";
 139                 num-lanes = <4>;
 140                 bus-range = <0x0 0xff>;
 141                 ranges = <0x81000000 0x0 0x00000000 0x10 0x00020000 0x0 0x00010000   /* downstream I/O */
 142                           0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 143         };
 144
 145         pcie@3500000 {
 146                 compatible = "fsl,ls-pcie", "snps,dw-pcie";
 147                 reg = <0x00 0x03500000 0x0 0x80000   /* dbi registers */
 148                        0x00 0x03580000 0x0 0x80000   /* lut registers */
 149                        0x12 0x00000000 0x0 0x20000>; /* configuration space */
 150                 reg-names = "dbi", "lut", "config";
 151                 #address-cells = <3>;
 152                 #size-cells = <2>;
 153                 device_type = "pci";
 154                 num-lanes = <4>;
 155                 bus-range = <0x0 0xff>;
 156                 ranges = <0x81000000 0x0 0x00000000 0x12 0x00020000 0x0 0x00010000   /* downstream I/O */
 157                           0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 158         };
 159
 160         pcie@3600000 {
 161                 compatible = "fsl,ls-pcie", "snps,dw-pcie";
 162                 reg = <0x00 0x03600000 0x0 0x80000   /* dbi registers */
 163                        0x00 0x03680000 0x0 0x80000   /* lut registers */
 164                        0x14 0x00000000 0x0 0x20000>; /* configuration space */
 165                 reg-names = "dbi", "lut", "config";
 166                 #address-cells = <3>;
 167                 #size-cells = <2>;
 168                 device_type = "pci";
 169                 num-lanes = <8>;
 170                 bus-range = <0x0 0xff>;
 171                 ranges = <0x81000000 0x0 0x00000000 0x14 0x00020000 0x0 0x00010000   /* downstream I/O */
 172                           0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 173         };
 174
 175         pcie@3700000 {
 176                 compatible = "fsl,ls-pcie", "snps,dw-pcie";
 177                 reg = <0x00 0x03700000 0x0 0x80000   /* dbi registers */
 178                        0x00 0x03780000 0x0 0x80000   /* lut registers */
 179                        0x16 0x00000000 0x0 0x20000>; /* configuration space */
 180                 reg-names = "dbi", "lut", "config";
 181                 #address-cells = <3>;
 182                 #size-cells = <2>;
 183                 device_type = "pci";
 184                 num-lanes = <4>;
 185                 bus-range = <0x0 0xff>;
 186                 ranges = <0x81000000 0x0 0x00000000 0x16 0x00020000 0x0 0x00010000   /* downstream I/O */
 187                           0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 188         };
 189
 190         sata: sata@3200000 {
 191                         compatible = "fsl,ls2080a-ahci";
 192                         reg = <0x0 0x3200000 0x0 0x10000>;
 193                         interrupts = <0 133 0x4>; /* Level high type */
 194                         status = "disabled";
 195         };
 196
 197         fsl_mc: fsl-mc@80c000000 {
 198                 compatible = "fsl,qoriq-mc", "simple-mfd";
 199                 reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
 200                       <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
 201                 #address-cells = <3>;
 202                 #size-cells = <1>;
 203
 204                 /*
 205                  * Region type 0x0 - MC portals
 206                  * Region type 0x1 - QBMAN portals
 207                  */
 208                 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
 209                         0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
 210
 211                 dpmacs {
 212                         compatible = "simple-mfd";
 213                         #address-cells = <1>;
 214                         #size-cells = <0>;
 215
 216                         dpmac1: dpmac@1 {
 217                                 compatible = "fsl,qoriq-mc-dpmac";
 218                                 reg = <0x1>;
 219                                 status = "disabled";
 220                         };
 221
 222                         dpmac2: dpmac@2 {
 223                                 compatible = "fsl,qoriq-mc-dpmac";
 224                                 reg = <0x2>;
 225                                 status = "disabled";
 226                         };
 227
 228                         dpmac3: dpmac@3 {
 229                                 compatible = "fsl,qoriq-mc-dpmac";
 230                                 reg = <0x3>;
 231                                 status = "disabled";
 232                         };
 233
 234                         dpmac4: dpmac@4 {
 235                                 compatible = "fsl,qoriq-mc-dpmac";
 236                                 reg = <0x4>;
 237                                 status = "disabled";
 238                         };
 239
 240                         dpmac5: dpmac@5 {
 241                                 compatible = "fsl,qoriq-mc-dpmac";
 242                                 reg = <0x5>;
 243                                 status = "disabled";
 244                         };
 245
 246                         dpmac6: dpmac@6 {
 247                                 compatible = "fsl,qoriq-mc-dpmac";
 248                                 reg = <0x6>;
 249                                 status = "disabled";
 250                         };
 251
 252                         dpmac7: dpmac@7 {
 253                                 compatible = "fsl,qoriq-mc-dpmac";
 254                                 reg = <0x7>;
 255                                 status = "disabled";
 256                         };
 257
 258                         dpmac8: dpmac@8 {
 259                                 compatible = "fsl,qoriq-mc-dpmac";
 260                                 reg = <0x8>;
 261                                 status = "disabled";
 262                         };
 263                 };
 264         };
 265
 266         emdio1: mdio@8B96000 {
 267                 compatible = "fsl,ls-mdio";
 268                 reg = <0x0 0x8B96000 0x0 0x1000>;
 269                 #address-cells = <1>;
 270                 #size-cells = <0>;
 271                 status = "disabled";
 272         };
 273
 274         emdio2: mdio@8B97000 {
 275                 compatible = "fsl,ls-mdio";
 276                 reg = <0x0 0x8B97000 0x0 0x1000>;
 277                 #address-cells = <1>;
 278                 #size-cells = <0>;
 279                 status = "disabled";
 280         };
 281 };