1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * NXP ls2080a SOC common device tree source
6 * Copyright 2013-2015 Freescale Semiconductor, Inc.
10 compatible = "fsl,ls2080a";
11 interrupt-parent = <&gic>;
16 device_type = "memory";
17 reg = <0x00000000 0x80000000 0 0x80000000>;
18 /* DRAM space - 1, size : 2 GB DRAM */
21 gic: interrupt-controller@6000000 {
22 compatible = "arm,gic-v3";
23 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
24 <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
25 #interrupt-cells = <3>;
27 interrupts = <1 9 0x4>;
30 gic_lpi_base: syscon@0x80000000 {
31 compatible = "gic-lpi-base";
32 reg = <0x0 0x80000000 0x0 0x100000>;
33 max-gic-redistributors = <8>;
37 compatible = "arm,armv8-timer";
38 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
39 <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
40 <1 11 0x8>, /* Virtual PPI, active-low */
41 <1 10 0x8>; /* Hypervisor PPI, active-low */
44 serial0: serial@21c0500 {
45 device_type = "serial";
46 compatible = "fsl,ns16550", "ns16550a";
47 reg = <0x0 0x21c0500 0x0 0x100>;
48 clock-frequency = <0>; /* Updated by bootloader */
49 interrupts = <0 32 0x1>; /* edge triggered */
52 serial1: serial@21c0600 {
53 device_type = "serial";
54 compatible = "fsl,ns16550", "ns16550a";
55 reg = <0x0 0x21c0600 0x0 0x100>;
56 clock-frequency = <0>; /* Updated by bootloader */
57 interrupts = <0 32 0x1>; /* edge triggered */
62 compatible = "fsl,vf610-i2c";
65 reg = <0x0 0x2000000 0x0 0x10000>;
66 interrupts = <0 34 0x4>; /* Level high type */
71 compatible = "fsl,vf610-i2c";
74 reg = <0x0 0x2010000 0x0 0x10000>;
75 interrupts = <0 34 0x4>; /* Level high type */
80 compatible = "fsl,vf610-i2c";
83 reg = <0x0 0x2020000 0x0 0x10000>;
84 interrupts = <0 35 0x4>; /* Level high type */
89 compatible = "fsl,vf610-i2c";
92 reg = <0x0 0x2030000 0x0 0x10000>;
93 interrupts = <0 35 0x4>; /* Level high type */
97 compatible = "fsl,vf610-dspi";
100 reg = <0x0 0x2100000 0x0 0x10000>;
101 interrupts = <0 26 0x4>; /* Level high type */
105 qspi: quadspi@1550000 {
106 compatible = "fsl,ls2080a-qspi";
107 #address-cells = <1>;
109 reg = <0x0 0x20c0000 0x0 0x10000>,
110 <0x0 0x20000000 0x0 0x10000000>;
111 reg-names = "QuadSPI", "QuadSPI-memory";
116 compatible = "fsl,esdhc";
117 reg = <0x0 0x2140000 0x0 0x10000>;
118 interrupts = <0 28 0x4>; /* Level high type */
124 compatible = "fsl,layerscape-dwc3";
125 reg = <0x0 0x3100000 0x0 0x10000>;
126 interrupts = <0 80 0x4>; /* Level high type */
131 compatible = "fsl,layerscape-dwc3";
132 reg = <0x0 0x3110000 0x0 0x10000>;
133 interrupts = <0 81 0x4>; /* Level high type */
137 pcie1: pcie@3400000 {
138 compatible = "fsl,ls-pcie", "snps,dw-pcie";
139 reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
140 0x00 0x03480000 0x0 0x80000 /* lut registers */
141 0x10 0x00000000 0x0 0x20000>; /* configuration space */
142 reg-names = "dbi", "lut", "config";
143 #address-cells = <3>;
147 bus-range = <0x0 0xff>;
148 ranges = <0x81000000 0x0 0x00000000 0x10 0x00020000 0x0 0x00010000 /* downstream I/O */
149 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
152 pcie2: pcie@3500000 {
153 compatible = "fsl,ls-pcie", "snps,dw-pcie";
154 reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
155 0x00 0x03580000 0x0 0x80000 /* lut registers */
156 0x12 0x00000000 0x0 0x20000>; /* configuration space */
157 reg-names = "dbi", "lut", "config";
158 #address-cells = <3>;
162 bus-range = <0x0 0xff>;
163 ranges = <0x81000000 0x0 0x00000000 0x12 0x00020000 0x0 0x00010000 /* downstream I/O */
164 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
167 pcie3: pcie@3600000 {
168 compatible = "fsl,ls-pcie", "snps,dw-pcie";
169 reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
170 0x00 0x03680000 0x0 0x80000 /* lut registers */
171 0x14 0x00000000 0x0 0x20000>; /* configuration space */
172 reg-names = "dbi", "lut", "config";
173 #address-cells = <3>;
177 bus-range = <0x0 0xff>;
178 ranges = <0x81000000 0x0 0x00000000 0x14 0x00020000 0x0 0x00010000 /* downstream I/O */
179 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
182 pcie4: pcie@3700000 {
183 compatible = "fsl,ls-pcie", "snps,dw-pcie";
184 reg = <0x00 0x03700000 0x0 0x80000 /* dbi registers */
185 0x00 0x03780000 0x0 0x80000 /* lut registers */
186 0x16 0x00000000 0x0 0x20000>; /* configuration space */
187 reg-names = "dbi", "lut", "config";
188 #address-cells = <3>;
192 bus-range = <0x0 0xff>;
193 ranges = <0x81000000 0x0 0x00000000 0x16 0x00020000 0x0 0x00010000 /* downstream I/O */
194 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
198 compatible = "fsl,ls2080a-ahci";
199 reg = <0x0 0x3200000 0x0 0x10000>;
200 interrupts = <0 133 0x4>; /* Level high type */
204 fsl_mc: fsl-mc@80c000000 {
205 compatible = "fsl,qoriq-mc", "simple-mfd";
206 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
207 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
208 #address-cells = <3>;
212 * Region type 0x0 - MC portals
213 * Region type 0x1 - QBMAN portals
215 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
216 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
219 compatible = "simple-mfd";
220 #address-cells = <1>;
224 compatible = "fsl,qoriq-mc-dpmac";
230 compatible = "fsl,qoriq-mc-dpmac";
236 compatible = "fsl,qoriq-mc-dpmac";
242 compatible = "fsl,qoriq-mc-dpmac";
248 compatible = "fsl,qoriq-mc-dpmac";
254 compatible = "fsl,qoriq-mc-dpmac";
260 compatible = "fsl,qoriq-mc-dpmac";
266 compatible = "fsl,qoriq-mc-dpmac";
273 emdio1: mdio@8B96000 {
274 compatible = "fsl,ls-mdio";
275 reg = <0x0 0x8B96000 0x0 0x1000>;
276 #address-cells = <1>;
281 emdio2: mdio@8B97000 {
282 compatible = "fsl,ls-mdio";
283 reg = <0x0 0x8B97000 0x0 0x1000>;
284 #address-cells = <1>;