arch/arm/dts/fsl-ls2080a.dtsi

   1 /*
   2  * Freescale ls2080a SOC common device tree source
   3  *
   4  * Copyright 2013-2015 Freescale Semiconductor, Inc.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 / {
  10         compatible = "fsl,ls2080a";
  11         interrupt-parent = <&gic>;
  12         #address-cells = <2>;
  13         #size-cells = <2>;
  14
  15         cpus {
  16                 #address-cells = <2>;
  17                 #size-cells = <0>;
  18
  19                 /*
  20                  * We expect the enable-method for cpu's to be "psci", but this
  21                  * is dependent on the SoC FW, which will fill this in.
  22                  *
  23                  * Currently supported enable-method is psci v0.2
  24                  */
  25
  26                 /* We have 4 clusters having 2 Cortex-A57 cores each */
  27                 cpu@0 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a57";
  30                         reg = <0x0 0x0>;
  31                 };
  32
  33                 cpu@1 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a57";
  36                         reg = <0x0 0x1>;
  37                 };
  38
  39                 cpu@100 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a57";
  42                         reg = <0x0 0x100>;
  43                 };
  44
  45                 cpu@101 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a57";
  48                         reg = <0x0 0x101>;
  49                 };
  50
  51                 cpu@200 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a57";
  54                         reg = <0x0 0x200>;
  55                 };
  56
  57                 cpu@201 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a57";
  60                         reg = <0x0 0x201>;
  61                 };
  62
  63                 cpu@300 {
  64                         device_type = "cpu";
  65                         compatible = "arm,cortex-a57";
  66                         reg = <0x0 0x300>;
  67                 };
  68
  69                 cpu@301 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a57";
  72                         reg = <0x0 0x301>;
  73                 };
  74         };
  75
  76         memory@80000000 {
  77                 device_type = "memory";
  78                 reg = <0x00000000 0x80000000 0 0x80000000>;
  79                       /* DRAM space - 1, size : 2 GB DRAM */
  80         };
  81
  82         gic: interrupt-controller@6000000 {
  83                 compatible = "arm,gic-v3";
  84                 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
  85                       <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
  86                 #interrupt-cells = <3>;
  87                 interrupt-controller;
  88                 interrupts = <1 9 0x4>;
  89         };
  90
  91         timer {
  92                 compatible = "arm,armv8-timer";
  93                 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
  94                              <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
  95                              <1 11 0x8>, /* Virtual PPI, active-low */
  96                              <1 10 0x8>; /* Hypervisor PPI, active-low */
  97         };
  98
  99         serial0: serial@21c0500 {
 100                 device_type = "serial";
 101                 compatible = "fsl,ns16550", "ns16550a";
 102                 reg = <0x0 0x21c0500 0x0 0x100>;
 103                 clock-frequency = <0>;  /* Updated by bootloader */
 104                 interrupts = <0 32 0x1>; /* edge triggered */
 105         };
 106
 107         serial1: serial@21c0600 {
 108                 device_type = "serial";
 109                 compatible = "fsl,ns16550", "ns16550a";
 110                 reg = <0x0 0x21c0600 0x0 0x100>;
 111                 clock-frequency = <0>;  /* Updated by bootloader */
 112                 interrupts = <0 32 0x1>; /* edge triggered */
 113         };
 114
 115         fsl_mc: fsl-mc@80c000000 {
 116                 compatible = "fsl,qoriq-mc";
 117                 reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
 118                       <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
 119         };
 120
 121         dspi: dspi@2100000 {
 122                 compatible = "fsl,vf610-dspi";
 123                 #address-cells = <1>;
 124                 #size-cells = <0>;
 125                 reg = <0x0 0x2100000 0x0 0x10000>;
 126                 interrupts = <0 26 0x4>; /* Level high type */
 127                 num-cs = <6>;
 128         };
 129
 130         qspi: quadspi@1550000 {
 131                 compatible = "fsl,vf610-qspi";
 132                 #address-cells = <1>;
 133                 #size-cells = <0>;
 134                 reg = <0x0 0x20c0000 0x0 0x10000>,
 135                         <0x0 0x20000000 0x0 0x10000000>;
 136                 reg-names = "QuadSPI", "QuadSPI-memory";
 137                 num-cs = <4>;
 138         };
 139 };