arch/arm/dts/fsl-ls2080a.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * NXP ls2080a SOC common device tree source
   4  *
   5  * Copyright 2020-2021 NXP
   6  * Copyright 2013-2015 Freescale Semiconductor, Inc.
   7  */
   8
   9 / {
  10         compatible = "fsl,ls2080a";
  11         interrupt-parent = <&gic>;
  12         #address-cells = <2>;
  13         #size-cells = <2>;
  14
  15         memory@80000000 {
  16                 device_type = "memory";
  17                 reg = <0x00000000 0x80000000 0 0x80000000>;
  18                       /* DRAM space - 1, size : 2 GB DRAM */
  19         };
  20
  21         gic: interrupt-controller@6000000 {
  22                 compatible = "arm,gic-v3";
  23                 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
  24                       <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
  25                 #interrupt-cells = <3>;
  26                 interrupt-controller;
  27                 interrupts = <1 9 0x4>;
  28         };
  29
  30         gic_lpi_base: syscon@0x80000000 {
  31                 compatible = "gic-lpi-base";
  32                 reg = <0x0 0x80000000 0x0 0x100000>;
  33                 max-gic-redistributors = <8>;
  34         };
  35
  36         timer {
  37                 compatible = "arm,armv8-timer";
  38                 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
  39                              <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
  40                              <1 11 0x8>, /* Virtual PPI, active-low */
  41                              <1 10 0x8>; /* Hypervisor PPI, active-low */
  42         };
  43
  44         serial0: serial@21c0500 {
  45                 device_type = "serial";
  46                 compatible = "fsl,ns16550", "ns16550a";
  47                 reg = <0x0 0x21c0500 0x0 0x100>;
  48                 clock-frequency = <0>;  /* Updated by bootloader */
  49                 interrupts = <0 32 0x1>; /* edge triggered */
  50         };
  51
  52         serial1: serial@21c0600 {
  53                 device_type = "serial";
  54                 compatible = "fsl,ns16550", "ns16550a";
  55                 reg = <0x0 0x21c0600 0x0 0x100>;
  56                 clock-frequency = <0>;  /* Updated by bootloader */
  57                 interrupts = <0 32 0x1>; /* edge triggered */
  58         };
  59
  60         i2c0: i2c@2000000 {
  61                 status = "disabled";
  62                 compatible = "fsl,vf610-i2c";
  63                 #address-cells = <1>;
  64                 #size-cells = <0>;
  65                 reg = <0x0 0x2000000 0x0 0x10000>;
  66                 interrupts = <0 34 0x4>; /* Level high type */
  67         };
  68
  69         i2c1: i2c@2010000 {
  70                 status = "disabled";
  71                 compatible = "fsl,vf610-i2c";
  72                 #address-cells = <1>;
  73                 #size-cells = <0>;
  74                 reg = <0x0 0x2010000 0x0 0x10000>;
  75                 interrupts = <0 34 0x4>; /* Level high type */
  76         };
  77
  78         i2c2: i2c@2020000 {
  79                 status = "disabled";
  80                 compatible = "fsl,vf610-i2c";
  81                 #address-cells = <1>;
  82                 #size-cells = <0>;
  83                 reg = <0x0 0x2020000 0x0 0x10000>;
  84                 interrupts = <0 35 0x4>; /* Level high type */
  85         };
  86
  87         i2c3: i2c@2030000 {
  88                 status = "disabled";
  89                 compatible = "fsl,vf610-i2c";
  90                 #address-cells = <1>;
  91                 #size-cells = <0>;
  92                 reg = <0x0 0x2030000 0x0 0x10000>;
  93                 interrupts = <0 35 0x4>; /* Level high type */
  94         };
  95
  96         dspi: dspi@2100000 {
  97                 compatible = "fsl,vf610-dspi";
  98                 #address-cells = <1>;
  99                 #size-cells = <0>;
 100                 reg = <0x0 0x2100000 0x0 0x10000>;
 101                 interrupts = <0 26 0x4>; /* Level high type */
 102                 num-cs = <6>;
 103         };
 104
 105         qspi: quadspi@1550000 {
 106                 compatible = "fsl,ls2080a-qspi";
 107                 #address-cells = <1>;
 108                 #size-cells = <0>;
 109                 reg = <0x0 0x20c0000 0x0 0x10000>,
 110                         <0x0 0x20000000 0x0 0x10000000>;
 111                 reg-names = "QuadSPI", "QuadSPI-memory";
 112                 status = "disabled";
 113         };
 114
 115         esdhc: esdhc@0 {
 116                 compatible = "fsl,esdhc";
 117                 reg = <0x0 0x2140000 0x0 0x10000>;
 118                 interrupts = <0 28 0x4>; /* Level high type */
 119                 little-endian;
 120                 bus-width = <4>;
 121         };
 122
 123         gpio0: gpio@2300000 {
 124                 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
 125                 reg = <0x0 0x2300000 0x0 0x10000>;
 126                 interrupts = <0 36 0x4>; /* Level high type */
 127                 gpio-controller;
 128                 little-endian;
 129                 #gpio-cells = <2>;
 130                 interrupt-controller;
 131                 #interrupt-cells = <2>;
 132         };
 133
 134         gpio1: gpio@2310000 {
 135                 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
 136                 reg = <0x0 0x2310000 0x0 0x10000>;
 137                 interrupts = <0 36 0x4>; /* Level high type */
 138                 gpio-controller;
 139                 little-endian;
 140                 #gpio-cells = <2>;
 141                 interrupt-controller;
 142                 #interrupt-cells = <2>;
 143         };
 144
 145         gpio2: gpio@2320000 {
 146                 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
 147                 reg = <0x0 0x2320000 0x0 0x10000>;
 148                 interrupts = <0 37 0x4>; /* Level high type */
 149                 gpio-controller;
 150                 little-endian;
 151                 #gpio-cells = <2>;
 152                 interrupt-controller;
 153                 #interrupt-cells = <2>;
 154         };
 155
 156         gpio3: gpio@2330000 {
 157                 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
 158                 reg = <0x0 0x2330000 0x0 0x10000>;
 159                 interrupts = <0 37 0x4>; /* Level high type */
 160                 gpio-controller;
 161                 little-endian;
 162                 #gpio-cells = <2>;
 163                 interrupt-controller;
 164                 #interrupt-cells = <2>;
 165         };
 166
 167         usb0: usb3@3100000 {
 168                 compatible = "fsl,layerscape-dwc3";
 169                 reg = <0x0 0x3100000 0x0 0x10000>;
 170                 interrupts = <0 80 0x4>; /* Level high type */
 171                 dr_mode = "host";
 172         };
 173
 174         usb1: usb3@3110000 {
 175                 compatible = "fsl,layerscape-dwc3";
 176                 reg = <0x0 0x3110000 0x0 0x10000>;
 177                 interrupts = <0 81 0x4>; /* Level high type */
 178                 dr_mode = "host";
 179         };
 180
 181         pcie1: pcie@3400000 {
 182                 compatible = "fsl,ls-pcie", "snps,dw-pcie";
 183                 reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
 184                        0x00 0x03480000 0x0 0x80000   /* lut registers */
 185                        0x10 0x00000000 0x0 0x20000>; /* configuration space */
 186                 reg-names = "dbi", "lut", "config";
 187                 #address-cells = <3>;
 188                 #size-cells = <2>;
 189                 device_type = "pci";
 190                 num-lanes = <4>;
 191                 bus-range = <0x0 0xff>;
 192                 ranges = <0x81000000 0x0 0x00000000 0x10 0x00020000 0x0 0x00010000   /* downstream I/O */
 193                           0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 194         };
 195
 196         pcie2: pcie@3500000 {
 197                 compatible = "fsl,ls-pcie", "snps,dw-pcie";
 198                 reg = <0x00 0x03500000 0x0 0x80000   /* dbi registers */
 199                        0x00 0x03580000 0x0 0x80000   /* lut registers */
 200                        0x12 0x00000000 0x0 0x20000>; /* configuration space */
 201                 reg-names = "dbi", "lut", "config";
 202                 #address-cells = <3>;
 203                 #size-cells = <2>;
 204                 device_type = "pci";
 205                 num-lanes = <4>;
 206                 bus-range = <0x0 0xff>;
 207                 ranges = <0x81000000 0x0 0x00000000 0x12 0x00020000 0x0 0x00010000   /* downstream I/O */
 208                           0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 209         };
 210
 211         pcie3: pcie@3600000 {
 212                 compatible = "fsl,ls-pcie", "snps,dw-pcie";
 213                 reg = <0x00 0x03600000 0x0 0x80000   /* dbi registers */
 214                        0x00 0x03680000 0x0 0x80000   /* lut registers */
 215                        0x14 0x00000000 0x0 0x20000>; /* configuration space */
 216                 reg-names = "dbi", "lut", "config";
 217                 #address-cells = <3>;
 218                 #size-cells = <2>;
 219                 device_type = "pci";
 220                 num-lanes = <8>;
 221                 bus-range = <0x0 0xff>;
 222                 ranges = <0x81000000 0x0 0x00000000 0x14 0x00020000 0x0 0x00010000   /* downstream I/O */
 223                           0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 224         };
 225
 226         pcie4: pcie@3700000 {
 227                 compatible = "fsl,ls-pcie", "snps,dw-pcie";
 228                 reg = <0x00 0x03700000 0x0 0x80000   /* dbi registers */
 229                        0x00 0x03780000 0x0 0x80000   /* lut registers */
 230                        0x16 0x00000000 0x0 0x20000>; /* configuration space */
 231                 reg-names = "dbi", "lut", "config";
 232                 #address-cells = <3>;
 233                 #size-cells = <2>;
 234                 device_type = "pci";
 235                 num-lanes = <4>;
 236                 bus-range = <0x0 0xff>;
 237                 ranges = <0x81000000 0x0 0x00000000 0x16 0x00020000 0x0 0x00010000   /* downstream I/O */
 238                           0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 239         };
 240
 241         sata: sata@3200000 {
 242                         compatible = "fsl,ls2080a-ahci";
 243                         reg = <0x0 0x3200000 0x0 0x10000>;
 244                         interrupts = <0 133 0x4>; /* Level high type */
 245                         status = "disabled";
 246         };
 247
 248         fsl_mc: fsl-mc@80c000000 {
 249                 compatible = "fsl,qoriq-mc", "simple-mfd";
 250                 reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
 251                       <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
 252                 #address-cells = <3>;
 253                 #size-cells = <1>;
 254
 255                 /*
 256                  * Region type 0x0 - MC portals
 257                  * Region type 0x1 - QBMAN portals
 258                  */
 259                 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
 260                         0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
 261
 262                 dpmacs {
 263                         compatible = "simple-mfd";
 264                         #address-cells = <1>;
 265                         #size-cells = <0>;
 266
 267                         dpmac1: dpmac@1 {
 268                                 compatible = "fsl,qoriq-mc-dpmac";
 269                                 reg = <0x1>;
 270                                 status = "disabled";
 271                         };
 272
 273                         dpmac2: dpmac@2 {
 274                                 compatible = "fsl,qoriq-mc-dpmac";
 275                                 reg = <0x2>;
 276                                 status = "disabled";
 277                         };
 278
 279                         dpmac3: dpmac@3 {
 280                                 compatible = "fsl,qoriq-mc-dpmac";
 281                                 reg = <0x3>;
 282                                 status = "disabled";
 283                         };
 284
 285                         dpmac4: dpmac@4 {
 286                                 compatible = "fsl,qoriq-mc-dpmac";
 287                                 reg = <0x4>;
 288                                 status = "disabled";
 289                         };
 290
 291                         dpmac5: dpmac@5 {
 292                                 compatible = "fsl,qoriq-mc-dpmac";
 293                                 reg = <0x5>;
 294                                 status = "disabled";
 295                         };
 296
 297                         dpmac6: dpmac@6 {
 298                                 compatible = "fsl,qoriq-mc-dpmac";
 299                                 reg = <0x6>;
 300                                 status = "disabled";
 301                         };
 302
 303                         dpmac7: dpmac@7 {
 304                                 compatible = "fsl,qoriq-mc-dpmac";
 305                                 reg = <0x7>;
 306                                 status = "disabled";
 307                         };
 308
 309                         dpmac8: dpmac@8 {
 310                                 compatible = "fsl,qoriq-mc-dpmac";
 311                                 reg = <0x8>;
 312                                 status = "disabled";
 313                         };
 314                 };
 315         };
 316
 317         emdio1: mdio@8B96000 {
 318                 compatible = "fsl,ls-mdio";
 319                 reg = <0x0 0x8B96000 0x0 0x1000>;
 320                 #address-cells = <1>;
 321                 #size-cells = <0>;
 322                 status = "disabled";
 323         };
 324
 325         emdio2: mdio@8B97000 {
 326                 compatible = "fsl,ls-mdio";
 327                 reg = <0x0 0x8B97000 0x0 0x1000>;
 328                 #address-cells = <1>;
 329                 #size-cells = <0>;
 330                 status = "disabled";
 331         };
 332 };