arch/arm/dts/fsl-ls1088a.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * NXP ls1088a SOC common device tree source
   4  *
   5  * Copyright 2017 NXP
   6  */
   7
   8 / {
   9         compatible = "fsl,ls1088a";
  10         interrupt-parent = <&gic>;
  11         #address-cells = <2>;
  12         #size-cells = <2>;
  13
  14         memory@80000000 {
  15                 device_type = "memory";
  16                 reg = <0x00000000 0x80000000 0 0x80000000>;
  17                       /* DRAM space - 1, size : 2 GB DRAM */
  18         };
  19
  20         gic: interrupt-controller@6000000 {
  21                 compatible = "arm,gic-v3";
  22                 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
  23                       <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
  24                 #interrupt-cells = <3>;
  25                 interrupt-controller;
  26                 interrupts = <1 9 0x4>;
  27         };
  28
  29         gic_lpi_base: syscon@0x80000000 {
  30                 compatible = "gic-lpi-base";
  31                 reg = <0x0 0x80000000 0x0 0x100000>;
  32                 max-gic-redistributors = <8>;
  33         };
  34
  35         timer {
  36                 compatible = "arm,armv8-timer";
  37                 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
  38                              <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
  39                              <1 11 0x8>, /* Virtual PPI, active-low */
  40                              <1 10 0x8>; /* Hypervisor PPI, active-low */
  41         };
  42
  43         i2c0: i2c@2000000 {
  44                 compatible = "fsl,vf610-i2c";
  45                 #address-cells = <1>;
  46                 #size-cells = <0>;
  47                 reg = <0x0 0x2000000 0x0 0x10000>;
  48                 interrupts = <0 34 4>;
  49         };
  50
  51         i2c1: i2c@2010000 {
  52                 compatible = "fsl,vf610-i2c";
  53                 #address-cells = <1>;
  54                 #size-cells = <0>;
  55                 reg = <0x0 0x2010000 0x0 0x10000>;
  56                 interrupts = <0 34 4>;
  57         };
  58
  59         i2c2: i2c@2020000 {
  60                 compatible = "fsl,vf610-i2c";
  61                 #address-cells = <1>;
  62                 #size-cells = <0>;
  63                 reg = <0x0 0x2020000 0x0 0x10000>;
  64                 interrupts = <0 35 4>;
  65         };
  66
  67         i2c3: i2c@2030000 {
  68                 compatible = "fsl,vf610-i2c";
  69                 #address-cells = <1>;
  70                 #size-cells = <0>;
  71                 reg = <0x0 0x2030000 0x0 0x10000>;
  72                 interrupts = <0 35 4>;
  73         };
  74
  75         serial0: serial@21c0500 {
  76                 device_type = "serial";
  77                 compatible = "fsl,ns16550", "ns16550a";
  78                 reg = <0x0 0x21c0500 0x0 0x100>;
  79                 clock-frequency = <0>;  /* Updated by bootloader */
  80                 interrupts = <0 32 0x1>; /* edge triggered */
  81         };
  82
  83         serial1: serial@21c0600 {
  84                 device_type = "serial";
  85                 compatible = "fsl,ns16550", "ns16550a";
  86                 reg = <0x0 0x21c0600 0x0 0x100>;
  87                 clock-frequency = <0>;  /* Updated by bootloader */
  88                 interrupts = <0 32 0x1>; /* edge triggered */
  89         };
  90
  91         dspi: dspi@2100000 {
  92                 compatible = "fsl,vf610-dspi";
  93                 #address-cells = <1>;
  94                 #size-cells = <0>;
  95                 reg = <0x0 0x2100000 0x0 0x10000>;
  96                 interrupts = <0 26 0x4>; /* Level high type */
  97                 num-cs = <6>;
  98         };
  99
 100         qspi: quadspi@1550000 {
 101                 compatible = "fsl,ls1088a-qspi";
 102                 #address-cells = <1>;
 103                 #size-cells = <0>;
 104                 reg = <0x0 0x20c0000 0x0 0x10000>,
 105                         <0x0 0x20000000 0x0 0x10000000>;
 106                 reg-names = "QuadSPI", "QuadSPI-memory";
 107                 num-cs = <4>;
 108         };
 109
 110         esdhc: esdhc@2140000 {
 111                 compatible = "fsl,esdhc";
 112                 reg = <0x0 0x2140000 0x0 0x10000>;
 113                 interrupts = <0 28 0x4>; /* Level high type */
 114                 little-endian;
 115                 bus-width = <4>;
 116         };
 117
 118         ifc: ifc@1530000 {
 119                 compatible = "fsl,ifc", "simple-bus";
 120                 reg = <0x0 0x2240000 0x0 0x20000>;
 121                 interrupts = <0 21 0x4>; /* Level high type */
 122         };
 123
 124         usb0: usb3@3100000 {
 125                 compatible = "fsl,layerscape-dwc3";
 126                 reg = <0x0 0x3100000 0x0 0x10000>;
 127                 interrupts = <0 80 0x4>; /* Level high type */
 128                 dr_mode = "host";
 129         };
 130
 131         usb1: usb3@3110000 {
 132                 compatible = "fsl,layerscape-dwc3";
 133                 reg = <0x0 0x3110000 0x0 0x10000>;
 134                 interrupts = <0 81 0x4>; /* Level high type */
 135                 dr_mode = "host";
 136         };
 137
 138         pcie@3400000 {
 139                 compatible = "fsl,ls-pcie", "snps,dw-pcie";
 140                 reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
 141                        0x00 0x03480000 0x0 0x80000   /* lut registers */
 142                        0x00 0x034c0000 0x0 0x40000   /* pf controls registers */
 143                        0x20 0x00000000 0x0 0x20000>; /* configuration space */
 144                 reg-names = "dbi", "lut", "ctrl", "config";
 145                 #address-cells = <3>;
 146                 #size-cells = <2>;
 147                 device_type = "pci";
 148                 num-lanes = <4>;
 149                 bus-range = <0x0 0xff>;
 150                 ranges = <0x81000000 0x0 0x00000000 0x20 0x00020000 0x0 0x00010000   /* downstream I/O */
 151                           0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 152         };
 153
 154         pcie@3500000 {
 155                 compatible = "fsl,ls-pcie", "snps,dw-pcie";
 156                 reg = <0x00 0x03500000 0x0 0x80000   /* dbi registers */
 157                        0x00 0x03580000 0x0 0x80000   /* lut registers */
 158                        0x00 0x035c0000 0x0 0x40000   /* pf controls registers */
 159                        0x28 0x00000000 0x0 0x20000>; /* configuration space */
 160                 reg-names = "dbi", "lut", "ctrl", "config";
 161                 #address-cells = <3>;
 162                 #size-cells = <2>;
 163                 device_type = "pci";
 164                 num-lanes = <4>;
 165                 bus-range = <0x0 0xff>;
 166                 ranges = <0x81000000 0x0 0x00000000 0x28 0x00020000 0x0 0x00010000   /* downstream I/O */
 167                           0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 168         };
 169
 170         pcie@3600000 {
 171                 compatible = "fsl,ls-pcie", "snps,dw-pcie";
 172                 reg = <0x00 0x03600000 0x0 0x80000   /* dbi registers */
 173                        0x00 0x03680000 0x0 0x80000   /* lut registers */
 174                        0x00 0x036c0000 0x0 0x40000   /* pf controls registers */
 175                        0x30 0x00000000 0x0 0x20000>; /* configuration space */
 176                 reg-names = "dbi", "lut", "ctrl", "config";
 177                 #address-cells = <3>;
 178                 #size-cells = <2>;
 179                 device_type = "pci";
 180                 num-lanes = <8>;
 181                 bus-range = <0x0 0xff>;
 182                 ranges = <0x81000000 0x0 0x00000000 0x30 0x00020000 0x0 0x00010000   /* downstream I/O */
 183                           0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 184         };
 185
 186         sata: sata@3200000 {
 187                 compatible = "fsl,ls1088a-ahci";
 188                 reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
 189                        0x7 0x100520  0x0 0x4>;   /* ecc sata addr*/
 190                 reg-names = "sata-base", "ecc-addr";
 191                 interrupts = <0 133 4>;
 192                 status = "disabled";
 193         };
 194
 195         psci {
 196                 compatible = "arm,psci-0.2";
 197                 method = "smc";
 198         };
 199
 200         fsl_mc: fsl-mc@80c000000 {
 201                 compatible = "fsl,qoriq-mc", "simple-mfd";
 202                 reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
 203                       <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
 204                 #address-cells = <3>;
 205                 #size-cells = <1>;
 206
 207                 /*
 208                  * Region type 0x0 - MC portals
 209                  * Region type 0x1 - QBMAN portals
 210                  */
 211                 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
 212                           0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
 213
 214                 dpmacs {
 215                         compatible = "simple-mfd";
 216                         #address-cells = <1>;
 217                         #size-cells = <0>;
 218
 219                         dpmac1: dpmac@1 {
 220                                 compatible = "fsl,qoriq-mc-dpmac";
 221                                 reg = <0x1>;
 222                                 status = "disabled";
 223                         };
 224
 225                         dpmac2: dpmac@2 {
 226                                 compatible = "fsl,qoriq-mc-dpmac";
 227                                 reg = <0x2>;
 228                                 status = "disabled";
 229                         };
 230
 231                         dpmac3: dpmac@3 {
 232                                 compatible = "fsl,qoriq-mc-dpmac";
 233                                 reg = <0x3>;
 234                                 status = "disabled";
 235                         };
 236
 237                         dpmac4: dpmac@4 {
 238                                 compatible = "fsl,qoriq-mc-dpmac";
 239                                 reg = <0x4>;
 240                                 status = "disabled";
 241                         };
 242
 243                         dpmac5: dpmac@5 {
 244                                 compatible = "fsl,qoriq-mc-dpmac";
 245                                 reg = <0x5>;
 246                                 status = "disabled";
 247                         };
 248
 249                         dpmac6: dpmac@6 {
 250                                 compatible = "fsl,qoriq-mc-dpmac";
 251                                 reg = <0x6>;
 252                                 status = "disabled";
 253                         };
 254
 255                         dpmac7: dpmac@7 {
 256                                 compatible = "fsl,qoriq-mc-dpmac";
 257                                 reg = <0x7>;
 258                                 status = "disabled";
 259                         };
 260
 261                         dpmac8: dpmac@8 {
 262                                 compatible = "fsl,qoriq-mc-dpmac";
 263                                 reg = <0x8>;
 264                                 status = "disabled";
 265                         };
 266
 267                         dpmac9: dpmac@9 {
 268                                 compatible = "fsl,qoriq-mc-dpmac";
 269                                 reg = <0x9>;
 270                                 status = "disabled";
 271                         };
 272
 273                         dpmac10: dpmac@a {
 274                                 compatible = "fsl,qoriq-mc-dpmac";
 275                                 reg = <0xa>;
 276                                 status = "disabled";
 277                         };
 278                 };
 279         };
 280
 281         emdio1: mdio@8B96000 {
 282                 compatible = "fsl,ls-mdio";
 283                 reg = <0x0 0x8B96000 0x0 0x1000>;
 284                 #address-cells = <1>;
 285                 #size-cells = <0>;
 286                 status = "disabled";
 287         };
 288
 289         emdio2: mdio@8B97000 {
 290                 compatible = "fsl,ls-mdio";
 291                 reg = <0x0 0x8B97000 0x0 0x1000>;
 292                 #address-cells = <1>;
 293                 #size-cells = <0>;
 294                 status = "disabled";
 295         };
 296 };