arch/arm/dts/fsl-ls1046a.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * Device Tree Include file for Freescale Layerscape-1046A family SoC.
   4  *
   5  * Copyright (C) 2016, Freescale Semiconductor
   6  * Copyright 2021 NXP
   7  *
   8  * Mingkai Hu <mingkai.hu@nxp.com>
   9  */
  10
  11 #include "skeleton64.dtsi"
  12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14
  15 / {
  16         compatible = "fsl,ls1046a";
  17         interrupt-parent = <&gic>;
  18
  19         sysclk: sysclk {
  20                 compatible = "fixed-clock";
  21                 #clock-cells = <0>;
  22                 clock-frequency = <100000000>;
  23                 clock-output-names = "sysclk";
  24         };
  25
  26         gic: interrupt-controller@1400000 {
  27                 compatible = "arm,gic-400";
  28                 #interrupt-cells = <3>;
  29                 interrupt-controller;
  30                 reg = <0x0 0x1410000 0 0x10000>, /* GICD */
  31                       <0x0 0x1420000 0 0x10000>, /* GICC */
  32                       <0x0 0x1440000 0 0x20000>, /* GICH */
  33                       <0x0 0x1460000 0 0x20000>; /* GICV */
  34                 interrupts = <1 9 0xf08>;
  35         };
  36
  37         soc: soc {
  38                 compatible = "simple-bus";
  39                 #address-cells = <2>;
  40                 #size-cells = <2>;
  41                 ranges;
  42
  43                 sfp: efuse@1e80000 {
  44                         compatible = "fsl,ls1021a-sfp";
  45                         reg = <0x0 0x1e80000 0x0 0x1000>;
  46                         clocks = <&clockgen 4 3>;
  47                         clock-names = "sfp";
  48                 };
  49
  50                 clockgen: clocking@1ee1000 {
  51                         compatible = "fsl,ls1046a-clockgen";
  52                         reg = <0x0 0x1ee1000 0x0 0x1000>;
  53                         #clock-cells = <2>;
  54                         clocks = <&sysclk>;
  55                 };
  56
  57                 dspi0: dspi@2100000 {
  58                         compatible = "fsl,vf610-dspi";
  59                         #address-cells = <1>;
  60                         #size-cells = <0>;
  61                         reg = <0x0 0x2100000 0x0 0x10000>;
  62                         interrupts = <0 64 0x4>;
  63                         clock-names = "dspi";
  64                         clocks = <&clockgen 4 0>;
  65                         spi-num-chipselects = <6>;
  66                         big-endian;
  67                         status = "disabled";
  68                 };
  69
  70                 dspi1: dspi@2110000 {
  71                         compatible = "fsl,vf610-dspi";
  72                         #address-cells = <1>;
  73                         #size-cells = <0>;
  74                         reg = <0x0 0x2110000 0x0 0x10000>;
  75                         interrupts = <0 65 0x4>;
  76                         clock-names = "dspi";
  77                         clocks = <&clockgen 4 0>;
  78                         spi-num-chipselects = <6>;
  79                         big-endian;
  80                         status = "disabled";
  81                 };
  82
  83                 esdhc: esdhc@1560000 {
  84                         compatible = "fsl,esdhc";
  85                         reg = <0x0 0x1560000 0x0 0x10000>;
  86                         interrupts = <0 62 0x4>;
  87                         big-endian;
  88                         bus-width = <4>;
  89                 };
  90
  91                 gpio0: gpio@2300000 {
  92                         compatible = "fsl,qoriq-gpio";
  93                         reg = <0x0 0x2300000 0x0 0x10000>;
  94                         interrupts = <0 66 4>;
  95                         gpio-controller;
  96                         #gpio-cells = <2>;
  97                         interrupt-controller;
  98                         #interrupt-cells = <2>;
  99                 };
 100
 101                 gpio1: gpio@2310000 {
 102                         compatible = "fsl,qoriq-gpio";
 103                         reg = <0x0 0x2310000 0x0 0x10000>;
 104                         interrupts = <0 67 4>;
 105                         gpio-controller;
 106                         #gpio-cells = <2>;
 107                         interrupt-controller;
 108                         #interrupt-cells = <2>;
 109                 };
 110
 111                 gpio2: gpio@2320000 {
 112                         compatible = "fsl,qoriq-gpio";
 113                         reg = <0x0 0x2320000 0x0 0x10000>;
 114                         interrupts = <0 68 4>;
 115                         gpio-controller;
 116                         #gpio-cells = <2>;
 117                         interrupt-controller;
 118                         #interrupt-cells = <2>;
 119                 };
 120
 121                 gpio3: gpio@2330000 {
 122                         compatible = "fsl,qoriq-gpio";
 123                         reg = <0x0 0x2330000 0x0 0x10000>;
 124                         interrupts = <0 134 4>;
 125                         gpio-controller;
 126                         #gpio-cells = <2>;
 127                         interrupt-controller;
 128                         #interrupt-cells = <2>;
 129                 };
 130
 131                 ifc: ifc@1530000 {
 132                         compatible = "fsl,ifc", "simple-bus";
 133                         reg = <0x0 0x1530000 0x0 0x10000>;
 134                         interrupts = <0 43 0x4>;
 135                 };
 136
 137                 crypto: crypto@1700000 {
 138                         compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
 139                                      "fsl,sec-v4.0";
 140                         fsl,sec-era = <8>;
 141                         #address-cells = <1>;
 142                         #size-cells = <1>;
 143                         ranges = <0x0 0x00 0x1700000 0x100000>;
 144                         reg = <0x00 0x1700000 0x0 0x100000>;
 145                         interrupts = <0 75 0x4>;
 146
 147                         sec_jr0: jr@10000 {
 148                                 compatible = "fsl,sec-v5.4-job-ring",
 149                                              "fsl,sec-v5.0-job-ring",
 150                                              "fsl,sec-v4.0-job-ring";
 151                                 reg        = <0x10000 0x10000>;
 152                                 interrupts = <0 71 0x4>;
 153                         };
 154
 155                         sec_jr1: jr@20000 {
 156                                 compatible = "fsl,sec-v5.4-job-ring",
 157                                              "fsl,sec-v5.0-job-ring",
 158                                              "fsl,sec-v4.0-job-ring";
 159                                 reg        = <0x20000 0x10000>;
 160                                 interrupts = <0 72 0x4>;
 161                         };
 162
 163                         sec_jr2: jr@30000 {
 164                                 compatible = "fsl,sec-v5.4-job-ring",
 165                                              "fsl,sec-v5.0-job-ring",
 166                                              "fsl,sec-v4.0-job-ring";
 167                                 reg        = <0x30000 0x10000>;
 168                                 interrupts = <0 73 0x4>;
 169                         };
 170
 171                         sec_jr3: jr@40000 {
 172                                 compatible = "fsl,sec-v5.4-job-ring",
 173                                              "fsl,sec-v5.0-job-ring",
 174                                              "fsl,sec-v4.0-job-ring";
 175                                 reg        = <0x40000 0x10000>;
 176                                 interrupts = <0 74 0x4>;
 177                         };
 178                 };
 179
 180                 i2c0: i2c@2180000 {
 181                         compatible = "fsl,vf610-i2c";
 182                         #address-cells = <1>;
 183                         #size-cells = <0>;
 184                         reg = <0x0 0x2180000 0x0 0x10000>;
 185                         interrupts = <0 56 0x4>;
 186                         clock-names = "i2c";
 187                         clocks = <&clockgen 4 0>;
 188                         status = "disabled";
 189                 };
 190
 191                 i2c1: i2c@2190000 {
 192                         compatible = "fsl,vf610-i2c";
 193                         #address-cells = <1>;
 194                         #size-cells = <0>;
 195                         reg = <0x0 0x2190000 0x0 0x10000>;
 196                         interrupts = <0 57 0x4>;
 197                         clock-names = "i2c";
 198                         clocks = <&clockgen 4 0>;
 199                         status = "disabled";
 200                 };
 201
 202                 i2c2: i2c@21a0000 {
 203                         compatible = "fsl,vf610-i2c";
 204                         #address-cells = <1>;
 205                         #size-cells = <0>;
 206                         reg = <0x0 0x21a0000 0x0 0x10000>;
 207                         interrupts = <0 58 0x4>;
 208                         clock-names = "i2c";
 209                         clocks = <&clockgen 4 0>;
 210                         status = "disabled";
 211                 };
 212
 213                 i2c3: i2c@21b0000 {
 214                         compatible = "fsl,vf610-i2c";
 215                         #address-cells = <1>;
 216                         #size-cells = <0>;
 217                         reg = <0x0 0x21b0000 0x0 0x10000>;
 218                         interrupts = <0 59 0x4>;
 219                         clock-names = "i2c";
 220                         clocks = <&clockgen 4 0>;
 221                         status = "disabled";
 222                 };
 223
 224                 duart0: serial@21c0500 {
 225                         compatible = "fsl,ns16550", "ns16550a";
 226                         reg = <0x00 0x21c0500 0x0 0x100>;
 227                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 228                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 229                                             QORIQ_CLK_PLL_DIV(2)>;
 230                         status = "disabled";
 231                 };
 232
 233                 duart1: serial@21c0600 {
 234                         compatible = "fsl,ns16550", "ns16550a";
 235                         reg = <0x00 0x21c0600 0x0 0x100>;
 236                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 237                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 238                                             QORIQ_CLK_PLL_DIV(2)>;
 239                         status = "disabled";
 240                 };
 241
 242                 duart2: serial@21d0500 {
 243                         compatible = "fsl,ns16550", "ns16550a";
 244                         reg = <0x0 0x21d0500 0x0 0x100>;
 245                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 246                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 247                                             QORIQ_CLK_PLL_DIV(2)>;
 248                         status = "disabled";
 249                 };
 250
 251                 duart3: serial@21d0600 {
 252                         compatible = "fsl,ns16550", "ns16550a";
 253                         reg = <0x0 0x21d0600 0x0 0x100>;
 254                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 255                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 256                                             QORIQ_CLK_PLL_DIV(2)>;
 257                         status = "disabled";
 258                 };
 259
 260                 lpuart0: serial@2950000 {
 261                         compatible = "fsl,ls1021a-lpuart";
 262                         reg = <0x0 0x2950000 0x0 0x1000>;
 263                         interrupts = <0 48 0x4>;
 264                         clocks = <&clockgen 4 0>;
 265                         clock-names = "ipg";
 266                         status = "disabled";
 267                 };
 268
 269                 lpuart1: serial@2960000 {
 270                         compatible = "fsl,ls1021a-lpuart";
 271                         reg = <0x0 0x2960000 0x0 0x1000>;
 272                         interrupts = <0 49 0x4>;
 273                         clocks = <&clockgen 4 1>;
 274                         clock-names = "ipg";
 275                         status = "disabled";
 276                 };
 277
 278                 lpuart2: serial@2970000 {
 279                         compatible = "fsl,ls1021a-lpuart";
 280                         reg = <0x0 0x2970000 0x0 0x1000>;
 281                         interrupts = <0 50 0x4>;
 282                         clocks = <&clockgen 4 1>;
 283                         clock-names = "ipg";
 284                         status = "disabled";
 285                 };
 286
 287                 lpuart3: serial@2980000 {
 288                         compatible = "fsl,ls1021a-lpuart";
 289                         reg = <0x0 0x2980000 0x0 0x1000>;
 290                         interrupts = <0 51 0x4>;
 291                         clocks = <&clockgen 4 1>;
 292                         clock-names = "ipg";
 293                         status = "disabled";
 294                 };
 295
 296                 lpuart4: serial@2990000 {
 297                         compatible = "fsl,ls1021a-lpuart";
 298                         reg = <0x0 0x2990000 0x0 0x1000>;
 299                         interrupts = <0 52 0x4>;
 300                         clocks = <&clockgen 4 1>;
 301                         clock-names = "ipg";
 302                         status = "disabled";
 303                 };
 304
 305                 lpuart5: serial@29a0000 {
 306                         compatible = "fsl,ls1021a-lpuart";
 307                         reg = <0x0 0x29a0000 0x0 0x1000>;
 308                         interrupts = <0 53 0x4>;
 309                         clocks = <&clockgen 4 1>;
 310                         clock-names = "ipg";
 311                         status = "disabled";
 312                 };
 313
 314                 qspi: quadspi@1550000 {
 315                         compatible = "fsl,ls1021a-qspi";
 316                         #address-cells = <1>;
 317                         #size-cells = <0>;
 318                         reg = <0x0 0x1550000 0x0 0x10000>,
 319                                 <0x0 0x40000000 0x0 0x10000000>;
 320                         reg-names = "QuadSPI", "QuadSPI-memory";
 321                         status = "disabled";
 322                 };
 323
 324                 usb0: usb@2f00000 {
 325                         compatible = "fsl,layerscape-dwc3";
 326                         reg = <0x0 0x2f00000 0x0 0x10000>;
 327                         interrupts = <0 60 4>;
 328                         dr_mode = "host";
 329                 };
 330
 331                 usb1: usb@3000000 {
 332                         compatible = "fsl,layerscape-dwc3";
 333                         reg = <0x0 0x3000000 0x0 0x10000>;
 334                         interrupts = <0 61 4>;
 335                         dr_mode = "host";
 336                 };
 337
 338                 usb2: usb@3100000 {
 339                         compatible = "fsl,layerscape-dwc3";
 340                         reg = <0x0 0x3100000 0x0 0x10000>;
 341                         interrupts = <0 63 4>;
 342                         dr_mode = "host";
 343                 };
 344
 345                 pcie1: pcie@3400000 {
 346                         compatible = "fsl,ls-pcie", "snps,dw-pcie";
 347                         reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
 348                                0x00 0x03480000 0x0 0x40000   /* lut registers */
 349                                0x00 0x034c0000 0x0 0x40000   /* pf controls registers */
 350                                0x40 0x00000000 0x0 0x20000>; /* configuration space */
 351                         reg-names = "dbi", "lut", "ctrl", "config";
 352                         big-endian;
 353                         #address-cells = <3>;
 354                         #size-cells = <2>;
 355                         device_type = "pci";
 356                         bus-range = <0x0 0xff>;
 357                         ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000   /* downstream I/O */
 358                                   0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 359                 };
 360
 361                 pcie_ep1: pcie_ep@3400000 {
 362                         compatible = "fsl,ls-pcie-ep";
 363                         reg = <0x00 0x03400000 0x0 0x80000
 364                                0x00 0x034c0000 0x0 0x40000
 365                                0x40 0x00000000 0x8 0x00000000>;
 366                         reg-names = "regs", "ctrl", "addr_space";
 367                         num-ib-windows = <6>;
 368                         num-ob-windows = <8>;
 369                         big-endian;
 370                 };
 371
 372                 pcie2: pcie@3500000 {
 373                         compatible = "fsl,ls-pcie", "snps,dw-pcie";
 374                         reg = <0x00 0x03500000 0x0 0x80000   /* dbi registers */
 375                                0x00 0x03580000 0x0 0x40000   /* lut registers */
 376                                0x00 0x035c0000 0x0 0x40000   /* pf controls registers */
 377                                0x48 0x00000000 0x0 0x20000>; /* configuration space */
 378                         reg-names = "dbi", "lut", "ctrl", "config";
 379                         big-endian;
 380                         #address-cells = <3>;
 381                         #size-cells = <2>;
 382                         device_type = "pci";
 383                         num-lanes = <2>;
 384                         bus-range = <0x0 0xff>;
 385                         ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000   /* downstream I/O */
 386                                   0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 387                 };
 388
 389                 pcie_ep2: pcie_ep@3500000 {
 390                         compatible = "fsl,ls-pcie-ep";
 391                         reg = <0x00 0x03500000 0x0 0x80000
 392                                0x00 0x035c0000 0x0 0x40000
 393                                0x48 0x00000000 0x8 0x00000000>;
 394                         reg-names = "regs", "ctrl", "addr_space";
 395                         num-ib-windows = <6>;
 396                         num-ob-windows = <8>;
 397                         big-endian;
 398                 };
 399
 400                 pcie3: pcie@3600000 {
 401                         compatible = "fsl,ls-pcie", "snps,dw-pcie";
 402                         reg = <0x00 0x03600000 0x0 0x80000   /* dbi registers */
 403                                0x00 0x03680000 0x0 0x40000   /* lut registers */
 404                                0x00 0x036c0000 0x0 0x40000   /* pf controls registers */
 405                                0x50 0x00000000 0x0 0x20000>; /* configuration space */
 406                         reg-names = "dbi", "lut", "ctrl", "config";
 407                         big-endian;
 408                         #address-cells = <3>;
 409                         #size-cells = <2>;
 410                         device_type = "pci";
 411                         bus-range = <0x0 0xff>;
 412                         ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000   /* downstream I/O */
 413                                   0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 414                 };
 415
 416                 pcie_ep3: pcie_ep@3600000 {
 417                         compatible = "fsl,ls-pcie-ep";
 418                         reg = <0x00 0x03600000 0x0 0x80000
 419                                0x00 0x036c0000 0x0 0x40000
 420                                0x50 0x00000000 0x8 0x00000000>;
 421                         reg-names = "regs", "ctrl", "addr_space";
 422                         num-ib-windows = <6>;
 423                         num-ob-windows = <8>;
 424                         big-endian;
 425                 };
 426
 427                 sata: sata@3200000 {
 428                         compatible = "fsl,ls1046a-ahci";
 429                         reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
 430                                0x0 0x20140520 0x0 0x4>;  /* ecc sata addr*/
 431                         reg-names = "ahci", "sata-ecc";
 432                         interrupts = <0 69 4>;
 433                         clocks = <&clockgen 4 1>;
 434                         status = "disabled";
 435                 };
 436         };
 437 };