2 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
4 * Copyright (C) 2014-2015, Freescale Semiconductor
6 * Mingkai Hu <Mingkai.hu@freescale.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
13 /include/ "skeleton64.dtsi"
16 compatible = "fsl,ls1043a";
17 interrupt-parent = <&gic>;
24 compatible = "arm,cortex-a53";
26 clocks = <&clockgen 1 0>;
31 compatible = "arm,cortex-a53";
33 clocks = <&clockgen 1 0>;
38 compatible = "arm,cortex-a53";
40 clocks = <&clockgen 1 0>;
45 compatible = "arm,cortex-a53";
47 clocks = <&clockgen 1 0>;
52 compatible = "fixed-clock";
54 clock-frequency = <100000000>;
55 clock-output-names = "sysclk";
58 gic: interrupt-controller@1400000 {
59 compatible = "arm,gic-400";
60 #interrupt-cells = <3>;
62 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
63 <0x0 0x1402000 0 0x2000>, /* GICC */
64 <0x0 0x1404000 0 0x2000>, /* GICH */
65 <0x0 0x1406000 0 0x2000>; /* GICV */
66 interrupts = <1 9 0xf08>;
70 compatible = "simple-bus";
75 clockgen: clocking@1ee1000 {
76 compatible = "fsl,ls1043a-clockgen";
77 reg = <0x0 0x1ee1000 0x0 0x1000>;
83 compatible = "fsl,vf610-dspi";
86 reg = <0x0 0x2100000 0x0 0x10000>;
87 interrupts = <0 64 0x4>;
89 clocks = <&clockgen 4 0>;
96 compatible = "fsl,vf610-dspi";
99 reg = <0x0 0x2110000 0x0 0x10000>;
100 interrupts = <0 65 0x4>;
101 clock-names = "dspi";
102 clocks = <&clockgen 4 0>;
109 compatible = "fsl,ifc", "simple-bus";
110 reg = <0x0 0x1530000 0x0 0x10000>;
111 interrupts = <0 43 0x4>;
115 compatible = "fsl,vf610-i2c";
116 #address-cells = <1>;
118 reg = <0x0 0x2180000 0x0 0x10000>;
119 interrupts = <0 56 0x4>;
121 clocks = <&clockgen 4 0>;
126 compatible = "fsl,vf610-i2c";
127 #address-cells = <1>;
129 reg = <0x0 0x2190000 0x0 0x10000>;
130 interrupts = <0 57 0x4>;
132 clocks = <&clockgen 4 0>;
137 compatible = "fsl,vf610-i2c";
138 #address-cells = <1>;
140 reg = <0x0 0x21a0000 0x0 0x10000>;
141 interrupts = <0 58 0x4>;
143 clocks = <&clockgen 4 0>;
148 compatible = "fsl,vf610-i2c";
149 #address-cells = <1>;
151 reg = <0x0 0x21b0000 0x0 0x10000>;
152 interrupts = <0 59 0x4>;
154 clocks = <&clockgen 4 0>;
158 duart0: serial@21c0500 {
159 compatible = "fsl,ns16550", "ns16550a";
160 reg = <0x00 0x21c0500 0x0 0x100>;
161 interrupts = <0 54 0x4>;
162 clocks = <&clockgen 4 0>;
165 duart1: serial@21c0600 {
166 compatible = "fsl,ns16550", "ns16550a";
167 reg = <0x00 0x21c0600 0x0 0x100>;
168 interrupts = <0 54 0x4>;
169 clocks = <&clockgen 4 0>;
172 duart2: serial@21d0500 {
173 compatible = "fsl,ns16550", "ns16550a";
174 reg = <0x0 0x21d0500 0x0 0x100>;
175 interrupts = <0 55 0x4>;
176 clocks = <&clockgen 4 0>;
179 duart3: serial@21d0600 {
180 compatible = "fsl,ns16550", "ns16550a";
181 reg = <0x0 0x21d0600 0x0 0x100>;
182 interrupts = <0 55 0x4>;
183 clocks = <&clockgen 4 0>;