1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
5 * Copyright 2020-2021 NXP
6 * Copyright (C) 2014-2015, Freescale Semiconductor
8 * Mingkai Hu <Mingkai.hu@freescale.com>
11 #include "skeleton64.dtsi"
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 compatible = "fsl,ls1043a";
17 interrupt-parent = <&gic>;
20 compatible = "fixed-clock";
22 clock-frequency = <100000000>;
23 clock-output-names = "sysclk";
26 gic: interrupt-controller@1400000 {
27 compatible = "arm,gic-400";
28 #interrupt-cells = <3>;
30 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
31 <0x0 0x1402000 0 0x2000>, /* GICC */
32 <0x0 0x1404000 0 0x2000>, /* GICH */
33 <0x0 0x1406000 0 0x2000>; /* GICV */
34 interrupts = <1 9 0xf08>;
38 compatible = "simple-bus";
44 compatible = "fsl,ls1021a-sfp";
45 reg = <0x0 0x1e80000 0x0 0x1000>;
46 clocks = <&clockgen 4 3>;
50 clockgen: clocking@1ee1000 {
51 compatible = "fsl,ls1043a-clockgen";
52 reg = <0x0 0x1ee1000 0x0 0x1000>;
58 compatible = "fsl,vf610-dspi";
61 reg = <0x0 0x2100000 0x0 0x10000>;
62 interrupts = <0 64 0x4>;
64 clocks = <&clockgen 4 0>;
65 spi-num-chipselects = <6>;
71 compatible = "fsl,vf610-dspi";
74 reg = <0x0 0x2110000 0x0 0x10000>;
75 interrupts = <0 65 0x4>;
77 clocks = <&clockgen 4 0>;
78 spi-num-chipselects = <6>;
83 esdhc: esdhc@1560000 {
84 compatible = "fsl,esdhc";
85 reg = <0x0 0x1560000 0x0 0x10000>;
86 interrupts = <0 62 0x4>;
92 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
93 reg = <0x0 0x2300000 0x0 0x10000>;
94 interrupts = <0 66 0x4>;
98 #interrupt-cells = <2>;
101 gpio1: gpio@2310000 {
102 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
103 reg = <0x0 0x2310000 0x0 0x10000>;
104 interrupts = <0 67 0x4>;
107 interrupt-controller;
108 #interrupt-cells = <2>;
111 gpio2: gpio@2320000 {
112 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
113 reg = <0x0 0x2320000 0x0 0x10000>;
114 interrupts = <0 68 0x4>;
117 interrupt-controller;
118 #interrupt-cells = <2>;
121 gpio3: gpio@2330000 {
122 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
123 reg = <0x0 0x2330000 0x0 0x10000>;
124 interrupts = <0 134 0x4>;
127 interrupt-controller;
128 #interrupt-cells = <2>;
132 compatible = "fsl,ifc", "simple-bus";
133 reg = <0x0 0x1530000 0x0 0x10000>;
134 interrupts = <0 43 0x4>;
137 crypto: crypto@1700000 {
138 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
141 #address-cells = <1>;
143 ranges = <0x0 0x00 0x1700000 0x100000>;
144 reg = <0x00 0x1700000 0x0 0x100000>;
145 interrupts = <0 75 0x4>;
148 compatible = "fsl,sec-v5.4-job-ring",
149 "fsl,sec-v5.0-job-ring",
150 "fsl,sec-v4.0-job-ring";
151 reg = <0x10000 0x10000>;
152 interrupts = <0 71 0x4>;
156 compatible = "fsl,sec-v5.4-job-ring",
157 "fsl,sec-v5.0-job-ring",
158 "fsl,sec-v4.0-job-ring";
159 reg = <0x20000 0x10000>;
160 interrupts = <0 72 0x4>;
164 compatible = "fsl,sec-v5.4-job-ring",
165 "fsl,sec-v5.0-job-ring",
166 "fsl,sec-v4.0-job-ring";
167 reg = <0x30000 0x10000>;
168 interrupts = <0 73 0x4>;
172 compatible = "fsl,sec-v5.4-job-ring",
173 "fsl,sec-v5.0-job-ring",
174 "fsl,sec-v4.0-job-ring";
175 reg = <0x40000 0x10000>;
176 interrupts = <0 74 0x4>;
181 compatible = "fsl,vf610-i2c";
182 #address-cells = <1>;
184 reg = <0x0 0x2180000 0x0 0x10000>;
185 interrupts = <0 56 0x4>;
187 clocks = <&clockgen 4 0>;
192 compatible = "fsl,vf610-i2c";
193 #address-cells = <1>;
195 reg = <0x0 0x2190000 0x0 0x10000>;
196 interrupts = <0 57 0x4>;
198 clocks = <&clockgen 4 0>;
203 compatible = "fsl,vf610-i2c";
204 #address-cells = <1>;
206 reg = <0x0 0x21a0000 0x0 0x10000>;
207 interrupts = <0 58 0x4>;
209 clocks = <&clockgen 4 0>;
214 compatible = "fsl,vf610-i2c";
215 #address-cells = <1>;
217 reg = <0x0 0x21b0000 0x0 0x10000>;
218 interrupts = <0 59 0x4>;
220 clocks = <&clockgen 4 0>;
224 duart0: serial@21c0500 {
225 compatible = "fsl,ns16550", "ns16550a";
226 reg = <0x00 0x21c0500 0x0 0x100>;
227 interrupts = <0 54 0x4>;
228 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
229 QORIQ_CLK_PLL_DIV(1)>;
232 duart1: serial@21c0600 {
233 compatible = "fsl,ns16550", "ns16550a";
234 reg = <0x00 0x21c0600 0x0 0x100>;
235 interrupts = <0 54 0x4>;
236 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
237 QORIQ_CLK_PLL_DIV(1)>;
240 duart2: serial@21d0500 {
241 compatible = "fsl,ns16550", "ns16550a";
242 reg = <0x0 0x21d0500 0x0 0x100>;
243 interrupts = <0 55 0x4>;
244 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
245 QORIQ_CLK_PLL_DIV(1)>;
248 duart3: serial@21d0600 {
249 compatible = "fsl,ns16550", "ns16550a";
250 reg = <0x0 0x21d0600 0x0 0x100>;
251 interrupts = <0 55 0x4>;
252 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
253 QORIQ_CLK_PLL_DIV(1)>;
256 lpuart0: serial@2950000 {
257 compatible = "fsl,ls1021a-lpuart";
258 reg = <0x0 0x2950000 0x0 0x1000>;
259 interrupts = <0 48 0x4>;
265 lpuart1: serial@2960000 {
266 compatible = "fsl,ls1021a-lpuart";
267 reg = <0x0 0x2960000 0x0 0x1000>;
268 interrupts = <0 49 0x4>;
274 lpuart2: serial@2970000 {
275 compatible = "fsl,ls1021a-lpuart";
276 reg = <0x0 0x2970000 0x0 0x1000>;
277 interrupts = <0 50 0x4>;
283 lpuart3: serial@2980000 {
284 compatible = "fsl,ls1021a-lpuart";
285 reg = <0x0 0x2980000 0x0 0x1000>;
286 interrupts = <0 51 0x4>;
292 lpuart4: serial@2990000 {
293 compatible = "fsl,ls1021a-lpuart";
294 reg = <0x0 0x2990000 0x0 0x1000>;
295 interrupts = <0 52 0x4>;
301 lpuart5: serial@29a0000 {
302 compatible = "fsl,ls1021a-lpuart";
303 reg = <0x0 0x29a0000 0x0 0x1000>;
304 interrupts = <0 53 0x4>;
309 qspi: quadspi@1550000 {
310 compatible = "fsl,ls1021a-qspi";
311 #address-cells = <1>;
313 reg = <0x0 0x1550000 0x0 0x10000>,
314 <0x0 0x40000000 0x0 0x1000000>;
315 reg-names = "QuadSPI", "QuadSPI-memory";
320 compatible = "fsl,layerscape-dwc3";
321 reg = <0x0 0x2f00000 0x0 0x10000>;
322 interrupts = <0 60 0x4>;
327 compatible = "fsl,layerscape-dwc3";
328 reg = <0x0 0x3000000 0x0 0x10000>;
329 interrupts = <0 61 0x4>;
334 compatible = "fsl,layerscape-dwc3";
335 reg = <0x0 0x3100000 0x0 0x10000>;
336 interrupts = <0 63 0x4>;
340 pcie1: pcie@3400000 {
341 compatible = "fsl,ls-pcie", "snps,dw-pcie";
342 reg = <0x00 0x03400000 0x0 0x10000 /* dbi registers */
343 0x00 0x03410000 0x0 0x10000 /* lut registers */
344 0x40 0x00000000 0x0 0x20000>; /* configuration space */
345 reg-names = "dbi", "lut", "config";
347 #address-cells = <3>;
350 bus-range = <0x0 0xff>;
351 ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */
352 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
355 pcie2: pcie@3500000 {
356 compatible = "fsl,ls-pcie", "snps,dw-pcie";
357 reg = <0x00 0x03500000 0x0 0x10000 /* dbi registers */
358 0x00 0x03510000 0x0 0x10000 /* lut registers */
359 0x48 0x00000000 0x0 0x20000>; /* configuration space */
360 reg-names = "dbi", "lut", "config";
362 #address-cells = <3>;
366 bus-range = <0x0 0xff>;
367 ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000 /* downstream I/O */
368 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
371 pcie3: pcie@3600000 {
372 compatible = "fsl,ls-pcie", "snps,dw-pcie";
373 reg = <0x00 0x03600000 0x0 0x10000 /* dbi registers */
374 0x00 0x03610000 0x0 0x10000 /* lut registers */
375 0x50 0x00000000 0x0 0x20000>; /* configuration space */
376 reg-names = "dbi", "lut", "config";
378 #address-cells = <3>;
381 bus-range = <0x0 0xff>;
382 ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000 /* downstream I/O */
383 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
387 compatible = "fsl,ls1043a-ahci";
388 reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
389 0x0 0x20140520 0x0 0x4>; /* ecc sata addr*/
390 reg-names = "ahci", "sata-ecc";
391 interrupts = <0 69 4>;
392 clocks = <&clockgen 4 0>;