1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * NXP ls1028a SOC common device tree source
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "fsl,ls1028a";
13 interrupt-parent = <&gic>;
18 compatible = "fixed-clock";
20 clock-frequency = <100000000>;
21 clock-output-names = "sysclk";
24 clockgen: clocking@1300000 {
25 compatible = "fsl,ls1028a-clockgen";
26 reg = <0x0 0x1300000 0x0 0xa0000>;
32 device_type = "memory";
33 reg = <0x00000000 0x01080000 0 0x80000000>;
34 /* DRAM space - 1, size : 2 GB DRAM */
37 gic: interrupt-controller@6000000 {
38 compatible = "arm,gic-v3";
39 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
40 <0x0 0x06040000 0 0x40000>;
41 #interrupt-cells = <3>;
43 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
47 gic_lpi_base: syscon@0x80000000 {
48 compatible = "gic-lpi-base";
49 reg = <0x0 0x80000000 0x0 0x100000>;
50 max-gic-redistributors = <2>;
54 compatible = "arm,armv8-timer";
55 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
57 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
59 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
61 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
65 fspi: flexspi@20c0000 {
66 compatible = "nxp,lx2160a-fspi";
69 reg = <0x0 0x20c0000 0x0 0x10000>,
70 <0x0 0x20000000 0x0 0x10000000>;
71 reg-names = "fspi_base", "fspi_mmap";
72 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
73 clock-names = "fspi_en", "fspi";
74 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
78 serial0: serial@21c0500 {
79 device_type = "serial";
80 compatible = "fsl,ns16550", "ns16550a";
81 reg = <0x0 0x21c0500 0x0 0x100>;
82 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
86 serial1: serial@21c0600 {
87 device_type = "serial";
88 compatible = "fsl,ns16550", "ns16550a";
89 reg = <0x0 0x21c0600 0x0 0x100>;
90 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
95 compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
96 reg = <0x00 0x03400000 0x0 0x80000
97 0x00 0x03480000 0x0 0x40000 /* lut registers */
98 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
99 0x80 0x00000000 0x0 0x20000>; /* configuration space */
100 reg-names = "dbi", "lut", "ctrl", "config";
101 #address-cells = <3>;
105 bus-range = <0x0 0xff>;
106 ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */
107 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
111 compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
112 reg = <0x00 0x03500000 0x0 0x80000
113 0x00 0x03580000 0x0 0x40000 /* lut registers */
114 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
115 0x88 0x00000000 0x0 0x20000>; /* configuration space */
116 reg-names = "dbi", "lut", "ctrl", "config";
117 #address-cells = <3>;
121 bus-range = <0x0 0xff>;
122 ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */
123 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
127 compatible = "pci-host-ecam-generic";
128 /* ECAM bus 0, HW has more space reserved but not populated */
129 bus-range = <0x0 0x0>;
130 reg = <0x01 0xf0000000 0x0 0x100000>;
131 #address-cells = <3>;
134 ranges= <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000>;
136 reg = <0x000000 0 0 0 0>;
140 reg = <0x000100 0 0 0 0>;
144 reg = <0x000200 0 0 0 0>;
146 phy-mode = "internal";
151 reg = <0x000300 0 0 0 0>;
155 reg = <0x000600 0 0 0 0>;
157 phy-mode = "internal";
162 compatible = "fsl,vf610-i2c";
163 #address-cells = <1>;
165 reg = <0x0 0x2000000 0x0 0x10000>;
166 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
168 clocks = <&clockgen 4 0>;
173 compatible = "fsl,vf610-i2c";
174 #address-cells = <1>;
176 reg = <0x0 0x2010000 0x0 0x10000>;
177 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
179 clocks = <&clockgen 4 0>;
184 compatible = "fsl,vf610-i2c";
185 #address-cells = <1>;
187 reg = <0x0 0x2020000 0x0 0x10000>;
188 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&clockgen 4 0>;
195 compatible = "fsl,vf610-i2c";
196 #address-cells = <1>;
198 reg = <0x0 0x2030000 0x0 0x10000>;
199 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&clockgen 4 0>;
206 compatible = "fsl,vf610-i2c";
207 #address-cells = <1>;
209 reg = <0x0 0x2040000 0x0 0x10000>;
210 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&clockgen 4 0>;
217 compatible = "fsl,vf610-i2c";
218 #address-cells = <1>;
220 reg = <0x0 0x2050000 0x0 0x10000>;
221 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&clockgen 4 0>;
228 compatible = "fsl,vf610-i2c";
229 #address-cells = <1>;
231 reg = <0x0 0x2060000 0x0 0x10000>;
232 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&clockgen 4 0>;
239 compatible = "fsl,vf610-i2c";
240 #address-cells = <1>;
242 reg = <0x0 0x2070000 0x0 0x10000>;
243 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&clockgen 4 0>;
249 lpuart0: serial@2260000 {
250 compatible = "fsl,ls1021a-lpuart";
251 reg = <0x0 0x2260000 0x0 0x1000>;
252 interrupts = <0 232 0x4>;
259 lpuart1: serial@2270000 {
260 compatible = "fsl,ls1021a-lpuart";
261 reg = <0x0 0x2270000 0x0 0x1000>;
262 interrupts = <0 233 0x4>;
269 lpuart2: serial@2280000 {
270 compatible = "fsl,ls1021a-lpuart";
271 reg = <0x0 0x2280000 0x0 0x1000>;
272 interrupts = <0 234 0x4>;
279 lpuart3: serial@2290000 {
280 compatible = "fsl,ls1021a-lpuart";
281 reg = <0x0 0x2290000 0x0 0x1000>;
282 interrupts = <0 235 0x4>;
289 lpuart4: serial@22a0000 {
290 compatible = "fsl,ls1021a-lpuart";
291 reg = <0x0 0x22a0000 0x0 0x1000>;
292 interrupts = <0 236 0x4>;
299 lpuart5: serial@22b0000 {
300 compatible = "fsl,ls1021a-lpuart";
301 reg = <0x0 0x22b0000 0x0 0x1000>;
302 interrupts = <0 237 0x4>;
310 compatible = "fsl,layerscape-dwc3";
311 reg = <0x0 0x3100000 0x0 0x10000>;
312 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
318 compatible = "fsl,layerscape-dwc3";
319 reg = <0x0 0x3110000 0x0 0x10000>;
320 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
325 dspi0: dspi@2100000 {
326 compatible = "fsl,vf610-dspi";
327 #address-cells = <1>;
329 reg = <0x0 0x2100000 0x0 0x10000>;
330 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
331 clock-names = "dspi";
332 clocks = <&clockgen 4 0>;
338 dspi1: dspi@2110000 {
339 compatible = "fsl,vf610-dspi";
340 #address-cells = <1>;
342 reg = <0x0 0x2110000 0x0 0x10000>;
343 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
344 clock-names = "dspi";
345 clocks = <&clockgen 4 0>;
351 dspi2: dspi@2120000 {
352 compatible = "fsl,vf610-dspi";
353 #address-cells = <1>;
355 reg = <0x0 0x2120000 0x0 0x10000>;
356 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
357 clock-names = "dspi";
358 clocks = <&clockgen 4 0>;
364 esdhc0: esdhc@2140000 {
365 compatible = "fsl,esdhc";
366 reg = <0x0 0x2140000 0x0 0x10000>;
367 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
373 esdhc1: esdhc@2150000 {
374 compatible = "fsl,esdhc";
375 reg = <0x0 0x2150000 0x0 0x10000>;
376 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
384 compatible = "fsl,ls1028a-ahci";
385 reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
386 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/
387 reg-names = "sata-base", "ecc-addr";
388 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
392 cluster1_core0_watchdog: wdt@c000000 {
393 compatible = "arm,sp805-wdt";
394 reg = <0x0 0xc000000 0x0 0x1000>;