1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * NXP ls1028a SOC common device tree source
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "fsl,ls1028a";
13 interrupt-parent = <&gic>;
18 compatible = "fixed-clock";
20 clock-frequency = <100000000>;
21 clock-output-names = "sysclk";
24 clockgen: clocking@1300000 {
25 compatible = "fsl,ls1028a-clockgen";
26 reg = <0x0 0x1300000 0x0 0xa0000>;
32 device_type = "memory";
33 reg = <0x00000000 0x01080000 0 0x80000000>;
34 /* DRAM space - 1, size : 2 GB DRAM */
37 gic: interrupt-controller@6000000 {
38 compatible = "arm,gic-v3";
39 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
40 <0x0 0x06040000 0 0x40000>;
41 #interrupt-cells = <3>;
43 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
48 compatible = "arm,armv8-timer";
49 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
51 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
53 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
55 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
59 fspi: flexspi@20c0000 {
60 compatible = "nxp,lx2160a-fspi";
63 reg = <0x0 0x20c0000 0x0 0x10000>,
64 <0x0 0x20000000 0x0 0x10000000>;
65 reg-names = "fspi_base", "fspi_mmap";
66 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
67 clock-names = "fspi_en", "fspi";
68 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
72 serial0: serial@21c0500 {
73 device_type = "serial";
74 compatible = "fsl,ns16550", "ns16550a";
75 reg = <0x0 0x21c0500 0x0 0x100>;
76 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
80 serial1: serial@21c0600 {
81 device_type = "serial";
82 compatible = "fsl,ns16550", "ns16550a";
83 reg = <0x0 0x21c0600 0x0 0x100>;
84 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
89 compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
90 reg = <0x00 0x03400000 0x0 0x80000
91 0x00 0x03480000 0x0 0x40000 /* lut registers */
92 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
93 0x80 0x00000000 0x0 0x20000>; /* configuration space */
94 reg-names = "dbi", "lut", "ctrl", "config";
99 bus-range = <0x0 0xff>;
100 ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */
101 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
105 compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
106 reg = <0x00 0x03500000 0x0 0x80000
107 0x00 0x03580000 0x0 0x40000 /* lut registers */
108 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
109 0x88 0x00000000 0x0 0x20000>; /* configuration space */
110 reg-names = "dbi", "lut", "ctrl", "config";
111 #address-cells = <3>;
115 bus-range = <0x0 0xff>;
116 ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */
117 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
121 compatible = "pci-host-ecam-generic";
122 /* ECAM bus 0, HW has more space reserved but not populated */
123 bus-range = <0x0 0x0>;
124 reg = <0x01 0xf0000000 0x0 0x100000>;
125 #address-cells = <3>;
128 ranges= <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000>;
130 reg = <0x000000 0 0 0 0>;
134 reg = <0x000100 0 0 0 0>;
138 reg = <0x000200 0 0 0 0>;
140 phy-mode = "internal";
145 reg = <0x000300 0 0 0 0>;
149 reg = <0x000600 0 0 0 0>;
151 phy-mode = "internal";
156 compatible = "fsl,vf610-i2c";
157 #address-cells = <1>;
159 reg = <0x0 0x2000000 0x0 0x10000>;
160 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
162 clocks = <&clockgen 4 0>;
167 compatible = "fsl,vf610-i2c";
168 #address-cells = <1>;
170 reg = <0x0 0x2010000 0x0 0x10000>;
171 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
173 clocks = <&clockgen 4 0>;
178 compatible = "fsl,vf610-i2c";
179 #address-cells = <1>;
181 reg = <0x0 0x2020000 0x0 0x10000>;
182 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
184 clocks = <&clockgen 4 0>;
189 compatible = "fsl,vf610-i2c";
190 #address-cells = <1>;
192 reg = <0x0 0x2030000 0x0 0x10000>;
193 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&clockgen 4 0>;
200 compatible = "fsl,vf610-i2c";
201 #address-cells = <1>;
203 reg = <0x0 0x2040000 0x0 0x10000>;
204 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
206 clocks = <&clockgen 4 0>;
211 compatible = "fsl,vf610-i2c";
212 #address-cells = <1>;
214 reg = <0x0 0x2050000 0x0 0x10000>;
215 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&clockgen 4 0>;
222 compatible = "fsl,vf610-i2c";
223 #address-cells = <1>;
225 reg = <0x0 0x2060000 0x0 0x10000>;
226 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&clockgen 4 0>;
233 compatible = "fsl,vf610-i2c";
234 #address-cells = <1>;
236 reg = <0x0 0x2070000 0x0 0x10000>;
237 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&clockgen 4 0>;
243 lpuart0: serial@2260000 {
244 compatible = "fsl,ls1021a-lpuart";
245 reg = <0x0 0x2260000 0x0 0x1000>;
246 interrupts = <0 232 0x4>;
253 lpuart1: serial@2270000 {
254 compatible = "fsl,ls1021a-lpuart";
255 reg = <0x0 0x2270000 0x0 0x1000>;
256 interrupts = <0 233 0x4>;
263 lpuart2: serial@2280000 {
264 compatible = "fsl,ls1021a-lpuart";
265 reg = <0x0 0x2280000 0x0 0x1000>;
266 interrupts = <0 234 0x4>;
273 lpuart3: serial@2290000 {
274 compatible = "fsl,ls1021a-lpuart";
275 reg = <0x0 0x2290000 0x0 0x1000>;
276 interrupts = <0 235 0x4>;
283 lpuart4: serial@22a0000 {
284 compatible = "fsl,ls1021a-lpuart";
285 reg = <0x0 0x22a0000 0x0 0x1000>;
286 interrupts = <0 236 0x4>;
293 lpuart5: serial@22b0000 {
294 compatible = "fsl,ls1021a-lpuart";
295 reg = <0x0 0x22b0000 0x0 0x1000>;
296 interrupts = <0 237 0x4>;
304 compatible = "fsl,layerscape-dwc3";
305 reg = <0x0 0x3100000 0x0 0x10000>;
306 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
312 compatible = "fsl,layerscape-dwc3";
313 reg = <0x0 0x3110000 0x0 0x10000>;
314 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
319 dspi0: dspi@2100000 {
320 compatible = "fsl,vf610-dspi";
321 #address-cells = <1>;
323 reg = <0x0 0x2100000 0x0 0x10000>;
324 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
325 clock-names = "dspi";
326 clocks = <&clockgen 4 0>;
332 dspi1: dspi@2110000 {
333 compatible = "fsl,vf610-dspi";
334 #address-cells = <1>;
336 reg = <0x0 0x2110000 0x0 0x10000>;
337 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
338 clock-names = "dspi";
339 clocks = <&clockgen 4 0>;
345 dspi2: dspi@2120000 {
346 compatible = "fsl,vf610-dspi";
347 #address-cells = <1>;
349 reg = <0x0 0x2120000 0x0 0x10000>;
350 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
351 clock-names = "dspi";
352 clocks = <&clockgen 4 0>;
358 esdhc0: esdhc@2140000 {
359 compatible = "fsl,esdhc";
360 reg = <0x0 0x2140000 0x0 0x10000>;
361 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
367 esdhc1: esdhc@2150000 {
368 compatible = "fsl,esdhc";
369 reg = <0x0 0x2150000 0x0 0x10000>;
370 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
378 compatible = "fsl,ls1028a-ahci";
379 reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
380 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/
381 reg-names = "sata-base", "ecc-addr";
382 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
386 cluster1_core0_watchdog: wdt@c000000 {
387 compatible = "arm,sp805-wdt";
388 reg = <0x0 0xc000000 0x0 0x1000>;