arch/arm/dts/fsl-ls1028a.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * NXP ls1028a SOC common device tree source
   4  *
   5  * Copyright 2019-2020 NXP
   6  *
   7  */
   8
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10
  11 / {
  12         compatible = "fsl,ls1028a";
  13         interrupt-parent = <&gic>;
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         sysclk: sysclk {
  18                 compatible = "fixed-clock";
  19                 #clock-cells = <0>;
  20                 clock-frequency = <100000000>;
  21                 clock-output-names = "sysclk";
  22         };
  23
  24         gic: interrupt-controller@6000000 {
  25                 compatible = "arm,gic-v3";
  26                 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
  27                           <0x0 0x06040000 0 0x40000>;
  28                 #interrupt-cells = <3>;
  29                 interrupt-controller;
  30                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
  31                                          IRQ_TYPE_LEVEL_LOW)>;
  32         };
  33
  34         timer {
  35                 compatible = "arm,armv8-timer";
  36                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
  37                                           IRQ_TYPE_LEVEL_LOW)>,
  38                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
  39                                           IRQ_TYPE_LEVEL_LOW)>,
  40                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
  41                                           IRQ_TYPE_LEVEL_LOW)>,
  42                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
  43                                           IRQ_TYPE_LEVEL_LOW)>;
  44         };
  45
  46         serial0: serial@21c0500 {
  47                 device_type = "serial";
  48                 compatible = "fsl,ns16550", "ns16550a";
  49                 reg = <0x0 0x21c0500 0x0 0x100>;
  50                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  51                 status = "disabled";
  52         };
  53
  54         serial1: serial@21c0600 {
  55                 device_type = "serial";
  56                 compatible = "fsl,ns16550", "ns16550a";
  57                 reg = <0x0 0x21c0600 0x0 0x100>;
  58                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  59                 status = "disabled";
  60         };
  61
  62         pcie1: pcie@3400000 {
  63                compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
  64                reg = <0x00 0x03400000 0x0 0x80000
  65                        0x00 0x03480000 0x0 0x40000   /* lut registers */
  66                        0x00 0x034c0000 0x0 0x40000  /* pf controls registers */
  67                        0x80 0x00000000 0x0 0x20000>; /* configuration space */
  68                reg-names = "dbi", "lut", "ctrl", "config";
  69                #address-cells = <3>;
  70                #size-cells = <2>;
  71                device_type = "pci";
  72                num-lanes = <4>;
  73                bus-range = <0x0 0xff>;
  74                ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000   /* downstream I/O */
  75                        0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  76         };
  77
  78         pcie2: pcie@3500000 {
  79                compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
  80                reg = <0x00 0x03500000 0x0 0x80000
  81                        0x00 0x03580000 0x0 0x40000   /* lut registers */
  82                        0x00 0x035c0000 0x0 0x40000  /* pf controls registers */
  83                        0x88 0x00000000 0x0 0x20000>; /* configuration space */
  84                reg-names = "dbi", "lut", "ctrl", "config";
  85                #address-cells = <3>;
  86                #size-cells = <2>;
  87                device_type = "pci";
  88                num-lanes = <4>;
  89                bus-range = <0x0 0xff>;
  90                ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000   /* downstream I/O */
  91                        0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  92         };
  93
  94         pcie@1f0000000 {
  95                 compatible = "pci-host-ecam-generic";
  96                 /* ECAM bus 0, HW has more space reserved but not populated */
  97                 bus-range = <0x0 0x0>;
  98                 reg = <0x01 0xf0000000 0x0 0x100000>;
  99                 #address-cells = <3>;
 100                 #size-cells = <2>;
 101                 device_type = "pci";
 102                 ranges= <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000>;
 103                 enetc0: pci@0,0 {
 104                         reg = <0x000000 0 0 0 0>;
 105                         status = "disabled";
 106                 };
 107                 enetc1: pci@0,1 {
 108                         reg = <0x000100 0 0 0 0>;
 109                         status = "disabled";
 110                 };
 111                 enetc2: pci@0,2 {
 112                         reg = <0x000200 0 0 0 0>;
 113                         status = "disabled";
 114                         phy-mode = "internal";
 115
 116                         fixed-link {
 117                                 speed = <2500>;
 118                                 full-duplex;
 119                         };
 120                 };
 121                 mdio0: pci@0,3 {
 122                         #address-cells=<0>;
 123                         #size-cells=<1>;
 124                         reg = <0x000300 0 0 0 0>;
 125                         status = "disabled";
 126
 127                         fixed-link {
 128                                 speed = <1000>;
 129                                 full-duplex;
 130                         };
 131                 };
 132
 133                 mscc_felix: pci@0,5 {
 134                         reg = <0x000500 0 0 0 0>;
 135                         status = "disabled";
 136
 137                         ports {
 138                                 #address-cells = <1>;
 139                                 #size-cells = <0>;
 140
 141                                 mscc_felix_port0: port@0 {
 142                                         reg = <0>;
 143                                         status = "disabled";
 144                                 };
 145
 146                                 mscc_felix_port1: port@1 {
 147                                         reg = <1>;
 148                                         status = "disabled";
 149                                 };
 150
 151                                 mscc_felix_port2: port@2 {
 152                                         reg = <2>;
 153                                         status = "disabled";
 154                                 };
 155
 156                                 mscc_felix_port3: port@3 {
 157                                         reg = <3>;
 158                                         status = "disabled";
 159                                 };
 160
 161                                 mscc_felix_port4: port@4 {
 162                                         reg = <4>;
 163                                         phy-mode = "internal";
 164                                         status = "disabled";
 165
 166                                         fixed-link {
 167                                                 speed = <2500>;
 168                                                 full-duplex;
 169                                         };
 170                                 };
 171
 172                                 mscc_felix_port5: port@5 {
 173                                         reg = <5>;
 174                                         phy-mode = "internal";
 175                                         status = "disabled";
 176
 177                                         fixed-link {
 178                                                 speed = <1000>;
 179                                                 full-duplex;
 180                                         };
 181
 182                                 };
 183                         };
 184                 };
 185
 186                 enetc6: pci@0,6 {
 187                         reg = <0x000600 0 0 0 0>;
 188                         status = "disabled";
 189                         phy-mode = "internal";
 190                 };
 191         };
 192
 193         lpuart0: serial@2260000 {
 194                 compatible = "fsl,ls1021a-lpuart";
 195                 reg = <0x0 0x2260000 0x0 0x1000>;
 196                 interrupts = <0 232 0x4>;
 197                 clocks = <&sysclk>;
 198                 clock-names = "ipg";
 199                 little-endian;
 200                 status = "disabled";
 201         };
 202
 203         lpuart1: serial@2270000 {
 204                 compatible = "fsl,ls1021a-lpuart";
 205                 reg = <0x0 0x2270000 0x0 0x1000>;
 206                 interrupts = <0 233 0x4>;
 207                 clocks = <&sysclk>;
 208                 clock-names = "ipg";
 209                 little-endian;
 210                 status = "disabled";
 211         };
 212
 213         lpuart2: serial@2280000 {
 214                 compatible = "fsl,ls1021a-lpuart";
 215                 reg = <0x0 0x2280000 0x0 0x1000>;
 216                 interrupts = <0 234 0x4>;
 217                 clocks = <&sysclk>;
 218                 clock-names = "ipg";
 219                 little-endian;
 220                 status = "disabled";
 221         };
 222
 223         lpuart3: serial@2290000 {
 224                 compatible = "fsl,ls1021a-lpuart";
 225                 reg = <0x0 0x2290000 0x0 0x1000>;
 226                 interrupts = <0 235 0x4>;
 227                 clocks = <&sysclk>;
 228                 clock-names = "ipg";
 229                 little-endian;
 230                 status = "disabled";
 231         };
 232
 233         lpuart4: serial@22a0000 {
 234                 compatible = "fsl,ls1021a-lpuart";
 235                 reg = <0x0 0x22a0000 0x0 0x1000>;
 236                 interrupts = <0 236 0x4>;
 237                 clocks = <&sysclk>;
 238                 clock-names = "ipg";
 239                 little-endian;
 240                 status = "disabled";
 241         };
 242
 243         lpuart5: serial@22b0000 {
 244                 compatible = "fsl,ls1021a-lpuart";
 245                 reg = <0x0 0x22b0000 0x0 0x1000>;
 246                 interrupts = <0 237 0x4>;
 247                 clocks = <&sysclk>;
 248                 clock-names = "ipg";
 249                 little-endian;
 250                 status = "disabled";
 251         };
 252
 253         usb1: usb3@3100000 {
 254                 compatible = "fsl,layerscape-dwc3";
 255                 reg = <0x0 0x3100000 0x0 0x10000>;
 256                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 257                 dr_mode = "host";
 258                 status = "disabled";
 259         };
 260
 261         usb2: usb3@3110000 {
 262                 compatible = "fsl,layerscape-dwc3";
 263                 reg = <0x0 0x3110000 0x0 0x10000>;
 264                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 265                 dr_mode = "host";
 266                 status = "disabled";
 267         };
 268
 269         dspi0: dspi@2100000 {
 270                 compatible = "fsl,vf610-dspi";
 271                 #address-cells = <1>;
 272                 #size-cells = <0>;
 273                 reg = <0x0 0x2100000 0x0 0x10000>;
 274                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 275                 clock-names = "dspi";
 276                 clocks = <&clockgen 4 0>;
 277                 num-cs = <5>;
 278                 litte-endian;
 279                 status = "disabled";
 280         };
 281
 282         dspi1: dspi@2110000 {
 283                 compatible = "fsl,vf610-dspi";
 284                 #address-cells = <1>;
 285                 #size-cells = <0>;
 286                 reg = <0x0 0x2110000 0x0 0x10000>;
 287                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 288                 clock-names = "dspi";
 289                 clocks = <&clockgen 4 0>;
 290                 num-cs = <5>;
 291                 little-endian;
 292                 status = "disabled";
 293         };
 294
 295         dspi2: dspi@2120000 {
 296                 compatible = "fsl,vf610-dspi";
 297                 #address-cells = <1>;
 298                 #size-cells = <0>;
 299                 reg = <0x0 0x2120000 0x0 0x10000>;
 300                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 301                 clock-names = "dspi";
 302                 clocks = <&clockgen 4 0>;
 303                 num-cs = <5>;
 304                 little-endian;
 305                 status = "disabled";
 306         };
 307
 308         esdhc0: esdhc@2140000 {
 309                 compatible = "fsl,esdhc";
 310                 reg = <0x0 0x2140000 0x0 0x10000>;
 311                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 312                 big-endian;
 313                 bus-width = <4>;
 314                 status = "disabled";
 315         };
 316
 317         esdhc1: esdhc@2150000 {
 318                 compatible = "fsl,esdhc";
 319                 reg = <0x0 0x2150000 0x0 0x10000>;
 320                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 321                 big-endian;
 322                 non-removable;
 323                 bus-width = <4>;
 324                 status = "disabled";
 325         };
 326
 327         gpio0: gpio@2300000 {
 328                 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
 329                 reg = <0x0 0x2300000 0x0 0x10000>;
 330                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 331                 gpio-controller;
 332                 #gpio-cells = <2>;
 333                 interrupt-controller;
 334                 #interrupt-cells = <2>;
 335                 little-endian;
 336         };
 337
 338         gpio1: gpio@2310000 {
 339                 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
 340                 reg = <0x0 0x2310000 0x0 0x10000>;
 341                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 342                 gpio-controller;
 343                 #gpio-cells = <2>;
 344                 interrupt-controller;
 345                 #interrupt-cells = <2>;
 346                 little-endian;
 347         };
 348
 349         gpio2: gpio@2320000 {
 350                 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
 351                 reg = <0x0 0x2320000 0x0 0x10000>;
 352                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 353                 gpio-controller;
 354                 #gpio-cells = <2>;
 355                 interrupt-controller;
 356                 #interrupt-cells = <2>;
 357                 little-endian;
 358         };
 359
 360         sata: sata@3200000 {
 361                 compatible = "fsl,ls1028a-ahci";
 362                 reg = <0x0 0x3200000 0x0 0x10000        /* ccsr sata base */
 363                        0x7 0x100520  0x0 0x4>;          /* ecc sata addr*/
 364                 reg-names = "sata-base", "ecc-addr";
 365                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 366                 status = "disabled";
 367         };
 368
 369         cluster1_core0_watchdog: wdt@c000000 {
 370                 compatible = "arm,sp805-wdt";
 371                 reg = <0x0 0xc000000 0x0 0x1000>;
 372         };
 373
 374         soc: soc {
 375                 compatible = "simple-bus";
 376                 #address-cells = <2>;
 377                 #size-cells = <2>;
 378                 ranges;
 379
 380                 clockgen: clocking@1300000 {
 381                         compatible = "fsl,ls1028a-clockgen";
 382                         reg = <0x0 0x1300000 0x0 0xa0000>;
 383                         #clock-cells = <2>;
 384                         clocks = <&sysclk>;
 385                 };
 386
 387                 i2c0: i2c@2000000 {
 388                         compatible = "fsl,vf610-i2c";
 389                         #address-cells = <1>;
 390                         #size-cells = <0>;
 391                         reg = <0x0 0x2000000 0x0 0x10000>;
 392                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 393                         clock-names = "i2c";
 394                         clocks = <&clockgen 4 0>;
 395                         status = "disabled";
 396                 };
 397
 398                 i2c1: i2c@2010000 {
 399                         compatible = "fsl,vf610-i2c";
 400                         #address-cells = <1>;
 401                         #size-cells = <0>;
 402                         reg = <0x0 0x2010000 0x0 0x10000>;
 403                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 404                         clock-names = "i2c";
 405                         clocks = <&clockgen 4 0>;
 406                         status = "disabled";
 407                 };
 408
 409                 i2c2: i2c@2020000 {
 410                         compatible = "fsl,vf610-i2c";
 411                         #address-cells = <1>;
 412                         #size-cells = <0>;
 413                         reg = <0x0 0x2020000 0x0 0x10000>;
 414                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 415                         clock-names = "i2c";
 416                         clocks = <&clockgen 4 0>;
 417                         status = "disabled";
 418                 };
 419
 420                 i2c3: i2c@2030000 {
 421                         compatible = "fsl,vf610-i2c";
 422                         #address-cells = <1>;
 423                         #size-cells = <0>;
 424                         reg = <0x0 0x2030000 0x0 0x10000>;
 425                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 426                         clock-names = "i2c";
 427                         clocks = <&clockgen 4 0>;
 428                         status = "disabled";
 429                 };
 430
 431                 i2c4: i2c@2040000 {
 432                         compatible = "fsl,vf610-i2c";
 433                         #address-cells = <1>;
 434                         #size-cells = <0>;
 435                         reg = <0x0 0x2040000 0x0 0x10000>;
 436                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 437                         clock-names = "i2c";
 438                         clocks = <&clockgen 4 0>;
 439                         status = "disabled";
 440                 };
 441
 442                 i2c5: i2c@2050000 {
 443                         compatible = "fsl,vf610-i2c";
 444                         #address-cells = <1>;
 445                         #size-cells = <0>;
 446                         reg = <0x0 0x2050000 0x0 0x10000>;
 447                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 448                         clock-names = "i2c";
 449                         clocks = <&clockgen 4 0>;
 450                         status = "disabled";
 451                 };
 452
 453                 i2c6: i2c@2060000 {
 454                         compatible = "fsl,vf610-i2c";
 455                         #address-cells = <1>;
 456                         #size-cells = <0>;
 457                         reg = <0x0 0x2060000 0x0 0x10000>;
 458                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 459                         clock-names = "i2c";
 460                         clocks = <&clockgen 4 0>;
 461                         status = "disabled";
 462                 };
 463
 464                 i2c7: i2c@2070000 {
 465                         compatible = "fsl,vf610-i2c";
 466                         #address-cells = <1>;
 467                         #size-cells = <0>;
 468                         reg = <0x0 0x2070000 0x0 0x10000>;
 469                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 470                         clock-names = "i2c";
 471                         clocks = <&clockgen 4 0>;
 472                         status = "disabled";
 473                 };
 474
 475                 fspi: flexspi@20c0000 {
 476                         compatible = "nxp,lx2160a-fspi";
 477                         #address-cells = <1>;
 478                         #size-cells = <0>;
 479                         reg = <0x0 0x20c0000 0x0 0x10000>,
 480                               <0x0 0x20000000 0x0 0x10000000>;
 481                         reg-names = "fspi_base", "fspi_mmap";
 482                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 483                         clock-names = "fspi_en", "fspi";
 484                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 485                         status = "disabled";
 486                 };
 487         };
 488 };