arch/arm/dts/fsl-ls1028a.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * NXP ls1028a SOC common device tree source
   4  *
   5  * Copyright 2019-2020 NXP
   6  *
   7  */
   8
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10
  11 / {
  12         compatible = "fsl,ls1028a";
  13         interrupt-parent = <&gic>;
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         sysclk: sysclk {
  18                 compatible = "fixed-clock";
  19                 #clock-cells = <0>;
  20                 clock-frequency = <100000000>;
  21                 clock-output-names = "sysclk";
  22         };
  23
  24         clockgen: clocking@1300000 {
  25                 compatible = "fsl,ls1028a-clockgen";
  26                 reg = <0x0 0x1300000 0x0 0xa0000>;
  27                 #clock-cells = <2>;
  28                 clocks = <&sysclk>;
  29         };
  30
  31         memory@01080000 {
  32                 device_type = "memory";
  33                 reg = <0x00000000 0x01080000 0 0x80000000>;
  34                       /* DRAM space - 1, size : 2 GB DRAM */
  35         };
  36
  37         gic: interrupt-controller@6000000 {
  38                 compatible = "arm,gic-v3";
  39                 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
  40                           <0x0 0x06040000 0 0x40000>;
  41                 #interrupt-cells = <3>;
  42                 interrupt-controller;
  43                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
  44                                          IRQ_TYPE_LEVEL_LOW)>;
  45         };
  46
  47         gic_lpi_base: syscon@0x80000000 {
  48                 compatible = "gic-lpi-base";
  49                 reg = <0x0 0x80000000 0x0 0x100000>;
  50                 max-gic-redistributors = <2>;
  51         };
  52
  53         timer {
  54                 compatible = "arm,armv8-timer";
  55                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
  56                                           IRQ_TYPE_LEVEL_LOW)>,
  57                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
  58                                           IRQ_TYPE_LEVEL_LOW)>,
  59                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
  60                                           IRQ_TYPE_LEVEL_LOW)>,
  61                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
  62                                           IRQ_TYPE_LEVEL_LOW)>;
  63         };
  64
  65         fspi: flexspi@20c0000 {
  66                 compatible = "nxp,lx2160a-fspi";
  67                 #address-cells = <1>;
  68                 #size-cells = <0>;
  69                 reg = <0x0 0x20c0000 0x0 0x10000>,
  70                       <0x0 0x20000000 0x0 0x10000000>;
  71                 reg-names = "fspi_base", "fspi_mmap";
  72                 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
  73                 clock-names = "fspi_en", "fspi";
  74                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  75                 status = "disabled";
  76         };
  77
  78         serial0: serial@21c0500 {
  79                 device_type = "serial";
  80                 compatible = "fsl,ns16550", "ns16550a";
  81                 reg = <0x0 0x21c0500 0x0 0x100>;
  82                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  83                 status = "disabled";
  84         };
  85
  86         serial1: serial@21c0600 {
  87                 device_type = "serial";
  88                 compatible = "fsl,ns16550", "ns16550a";
  89                 reg = <0x0 0x21c0600 0x0 0x100>;
  90                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  91                 status = "disabled";
  92         };
  93
  94         pcie1: pcie@3400000 {
  95                compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
  96                reg = <0x00 0x03400000 0x0 0x80000
  97                        0x00 0x03480000 0x0 0x40000   /* lut registers */
  98                        0x00 0x034c0000 0x0 0x40000  /* pf controls registers */
  99                        0x80 0x00000000 0x0 0x20000>; /* configuration space */
 100                reg-names = "dbi", "lut", "ctrl", "config";
 101                #address-cells = <3>;
 102                #size-cells = <2>;
 103                device_type = "pci";
 104                num-lanes = <4>;
 105                bus-range = <0x0 0xff>;
 106                ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000   /* downstream I/O */
 107                        0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 108         };
 109
 110         pcie2: pcie@3500000 {
 111                compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
 112                reg = <0x00 0x03500000 0x0 0x80000
 113                        0x00 0x03580000 0x0 0x40000   /* lut registers */
 114                        0x00 0x035c0000 0x0 0x40000  /* pf controls registers */
 115                        0x88 0x00000000 0x0 0x20000>; /* configuration space */
 116                reg-names = "dbi", "lut", "ctrl", "config";
 117                #address-cells = <3>;
 118                #size-cells = <2>;
 119                device_type = "pci";
 120                num-lanes = <4>;
 121                bus-range = <0x0 0xff>;
 122                ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000   /* downstream I/O */
 123                        0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 124         };
 125
 126         pcie@1f0000000 {
 127                 compatible = "pci-host-ecam-generic";
 128                 /* ECAM bus 0, HW has more space reserved but not populated */
 129                 bus-range = <0x0 0x0>;
 130                 reg = <0x01 0xf0000000 0x0 0x100000>;
 131                 #address-cells = <3>;
 132                 #size-cells = <2>;
 133                 device_type = "pci";
 134                 ranges= <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000>;
 135                 enetc0: pci@0,0 {
 136                         reg = <0x000000 0 0 0 0>;
 137                         status = "disabled";
 138                 };
 139                 enetc1: pci@0,1 {
 140                         reg = <0x000100 0 0 0 0>;
 141                         status = "disabled";
 142                 };
 143                 enetc2: pci@0,2 {
 144                         reg = <0x000200 0 0 0 0>;
 145                         status = "okay";
 146                         phy-mode = "internal";
 147
 148                         fixed-link {
 149                                 speed = <2500>;
 150                                 full-duplex;
 151                         };
 152                 };
 153                 mdio0: pci@0,3 {
 154                         #address-cells=<0>;
 155                         #size-cells=<1>;
 156                         reg = <0x000300 0 0 0 0>;
 157                         status = "disabled";
 158
 159                         fixed-link {
 160                                 speed = <1000>;
 161                                 full-duplex;
 162                         };
 163                 };
 164
 165                 mscc_felix: pci@0,5 {
 166                         reg = <0x000500 0 0 0 0>;
 167                         status = "disabled";
 168
 169                         ports {
 170                                 #address-cells = <1>;
 171                                 #size-cells = <0>;
 172
 173                                 mscc_felix_port0: port@0 {
 174                                         reg = <0>;
 175                                         status = "disabled";
 176                                 };
 177
 178                                 mscc_felix_port1: port@1 {
 179                                         reg = <1>;
 180                                         status = "disabled";
 181                                 };
 182
 183                                 mscc_felix_port2: port@2 {
 184                                         reg = <2>;
 185                                         status = "disabled";
 186                                 };
 187
 188                                 mscc_felix_port3: port@3 {
 189                                         reg = <3>;
 190                                         status = "disabled";
 191                                 };
 192
 193                                 mscc_felix_port4: port@4 {
 194                                         reg = <4>;
 195                                         phy-mode = "internal";
 196                                         status = "disabled";
 197
 198                                         fixed-link {
 199                                                 speed = <2500>;
 200                                                 full-duplex;
 201                                         };
 202                                 };
 203
 204                                 mscc_felix_port5: port@5 {
 205                                         reg = <5>;
 206                                         phy-mode = "internal";
 207                                         status = "disabled";
 208
 209                                         fixed-link {
 210                                                 speed = <1000>;
 211                                                 full-duplex;
 212                                         };
 213
 214                                 };
 215                         };
 216                 };
 217
 218                 enetc6: pci@0,6 {
 219                         reg = <0x000600 0 0 0 0>;
 220                         status = "disabled";
 221                         phy-mode = "internal";
 222                 };
 223         };
 224
 225         i2c0: i2c@2000000 {
 226                 compatible = "fsl,vf610-i2c";
 227                 #address-cells = <1>;
 228                 #size-cells = <0>;
 229                 reg = <0x0 0x2000000 0x0 0x10000>;
 230                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 231                 clock-names = "i2c";
 232                 clocks = <&clockgen 4 0>;
 233                 status = "disabled";
 234         };
 235
 236         i2c1: i2c@2010000 {
 237                 compatible = "fsl,vf610-i2c";
 238                 #address-cells = <1>;
 239                 #size-cells = <0>;
 240                 reg = <0x0 0x2010000 0x0 0x10000>;
 241                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 242                 clock-names = "i2c";
 243                 clocks = <&clockgen 4 0>;
 244                 status = "disabled";
 245         };
 246
 247         i2c2: i2c@2020000 {
 248                 compatible = "fsl,vf610-i2c";
 249                 #address-cells = <1>;
 250                 #size-cells = <0>;
 251                 reg = <0x0 0x2020000 0x0 0x10000>;
 252                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 253                 clock-names = "i2c";
 254                 clocks = <&clockgen 4 0>;
 255                 status = "disabled";
 256         };
 257
 258         i2c3: i2c@2030000 {
 259                 compatible = "fsl,vf610-i2c";
 260                 #address-cells = <1>;
 261                 #size-cells = <0>;
 262                 reg = <0x0 0x2030000 0x0 0x10000>;
 263                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 264                 clock-names = "i2c";
 265                 clocks = <&clockgen 4 0>;
 266                 status = "disabled";
 267         };
 268
 269         i2c4: i2c@2040000 {
 270                 compatible = "fsl,vf610-i2c";
 271                 #address-cells = <1>;
 272                 #size-cells = <0>;
 273                 reg = <0x0 0x2040000 0x0 0x10000>;
 274                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 275                 clock-names = "i2c";
 276                 clocks = <&clockgen 4 0>;
 277                 status = "disabled";
 278         };
 279
 280         i2c5: i2c@2050000 {
 281                 compatible = "fsl,vf610-i2c";
 282                 #address-cells = <1>;
 283                 #size-cells = <0>;
 284                 reg = <0x0 0x2050000 0x0 0x10000>;
 285                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 286                 clock-names = "i2c";
 287                 clocks = <&clockgen 4 0>;
 288                 status = "disabled";
 289         };
 290
 291         i2c6: i2c@2060000 {
 292                 compatible = "fsl,vf610-i2c";
 293                 #address-cells = <1>;
 294                 #size-cells = <0>;
 295                 reg = <0x0 0x2060000 0x0 0x10000>;
 296                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 297                 clock-names = "i2c";
 298                 clocks = <&clockgen 4 0>;
 299                 status = "disabled";
 300         };
 301
 302         i2c7: i2c@2070000 {
 303                 compatible = "fsl,vf610-i2c";
 304                 #address-cells = <1>;
 305                 #size-cells = <0>;
 306                 reg = <0x0 0x2070000 0x0 0x10000>;
 307                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 308                 clock-names = "i2c";
 309                 clocks = <&clockgen 4 0>;
 310                 status = "disabled";
 311         };
 312
 313         lpuart0: serial@2260000 {
 314                 compatible = "fsl,ls1021a-lpuart";
 315                 reg = <0x0 0x2260000 0x0 0x1000>;
 316                 interrupts = <0 232 0x4>;
 317                 clocks = <&sysclk>;
 318                 clock-names = "ipg";
 319                 little-endian;
 320                 status = "disabled";
 321         };
 322
 323         lpuart1: serial@2270000 {
 324                 compatible = "fsl,ls1021a-lpuart";
 325                 reg = <0x0 0x2270000 0x0 0x1000>;
 326                 interrupts = <0 233 0x4>;
 327                 clocks = <&sysclk>;
 328                 clock-names = "ipg";
 329                 little-endian;
 330                 status = "disabled";
 331         };
 332
 333         lpuart2: serial@2280000 {
 334                 compatible = "fsl,ls1021a-lpuart";
 335                 reg = <0x0 0x2280000 0x0 0x1000>;
 336                 interrupts = <0 234 0x4>;
 337                 clocks = <&sysclk>;
 338                 clock-names = "ipg";
 339                 little-endian;
 340                 status = "disabled";
 341         };
 342
 343         lpuart3: serial@2290000 {
 344                 compatible = "fsl,ls1021a-lpuart";
 345                 reg = <0x0 0x2290000 0x0 0x1000>;
 346                 interrupts = <0 235 0x4>;
 347                 clocks = <&sysclk>;
 348                 clock-names = "ipg";
 349                 little-endian;
 350                 status = "disabled";
 351         };
 352
 353         lpuart4: serial@22a0000 {
 354                 compatible = "fsl,ls1021a-lpuart";
 355                 reg = <0x0 0x22a0000 0x0 0x1000>;
 356                 interrupts = <0 236 0x4>;
 357                 clocks = <&sysclk>;
 358                 clock-names = "ipg";
 359                 little-endian;
 360                 status = "disabled";
 361         };
 362
 363         lpuart5: serial@22b0000 {
 364                 compatible = "fsl,ls1021a-lpuart";
 365                 reg = <0x0 0x22b0000 0x0 0x1000>;
 366                 interrupts = <0 237 0x4>;
 367                 clocks = <&sysclk>;
 368                 clock-names = "ipg";
 369                 little-endian;
 370                 status = "disabled";
 371         };
 372
 373         usb1: usb3@3100000 {
 374                 compatible = "fsl,layerscape-dwc3";
 375                 reg = <0x0 0x3100000 0x0 0x10000>;
 376                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 377                 dr_mode = "host";
 378                 status = "disabled";
 379         };
 380
 381         usb2: usb3@3110000 {
 382                 compatible = "fsl,layerscape-dwc3";
 383                 reg = <0x0 0x3110000 0x0 0x10000>;
 384                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 385                 dr_mode = "host";
 386                 status = "disabled";
 387         };
 388
 389         dspi0: dspi@2100000 {
 390                 compatible = "fsl,vf610-dspi";
 391                 #address-cells = <1>;
 392                 #size-cells = <0>;
 393                 reg = <0x0 0x2100000 0x0 0x10000>;
 394                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 395                 clock-names = "dspi";
 396                 clocks = <&clockgen 4 0>;
 397                 num-cs = <5>;
 398                 litte-endian;
 399                 status = "disabled";
 400         };
 401
 402         dspi1: dspi@2110000 {
 403                 compatible = "fsl,vf610-dspi";
 404                 #address-cells = <1>;
 405                 #size-cells = <0>;
 406                 reg = <0x0 0x2110000 0x0 0x10000>;
 407                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 408                 clock-names = "dspi";
 409                 clocks = <&clockgen 4 0>;
 410                 num-cs = <5>;
 411                 little-endian;
 412                 status = "disabled";
 413         };
 414
 415         dspi2: dspi@2120000 {
 416                 compatible = "fsl,vf610-dspi";
 417                 #address-cells = <1>;
 418                 #size-cells = <0>;
 419                 reg = <0x0 0x2120000 0x0 0x10000>;
 420                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 421                 clock-names = "dspi";
 422                 clocks = <&clockgen 4 0>;
 423                 num-cs = <5>;
 424                 little-endian;
 425                 status = "disabled";
 426         };
 427
 428         esdhc0: esdhc@2140000 {
 429                 compatible = "fsl,esdhc";
 430                 reg = <0x0 0x2140000 0x0 0x10000>;
 431                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 432                 big-endian;
 433                 bus-width = <4>;
 434                 status = "disabled";
 435         };
 436
 437         esdhc1: esdhc@2150000 {
 438                 compatible = "fsl,esdhc";
 439                 reg = <0x0 0x2150000 0x0 0x10000>;
 440                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 441                 big-endian;
 442                 non-removable;
 443                 bus-width = <4>;
 444                 status = "disabled";
 445         };
 446
 447         gpio0: gpio@2300000 {
 448                 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
 449                 reg = <0x0 0x2300000 0x0 0x10000>;
 450                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 451                 gpio-controller;
 452                 #gpio-cells = <2>;
 453                 interrupt-controller;
 454                 #interrupt-cells = <2>;
 455                 little-endian;
 456         };
 457
 458         gpio1: gpio@2310000 {
 459                 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
 460                 reg = <0x0 0x2310000 0x0 0x10000>;
 461                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 462                 gpio-controller;
 463                 #gpio-cells = <2>;
 464                 interrupt-controller;
 465                 #interrupt-cells = <2>;
 466                 little-endian;
 467         };
 468
 469         gpio2: gpio@2320000 {
 470                 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
 471                 reg = <0x0 0x2320000 0x0 0x10000>;
 472                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 473                 gpio-controller;
 474                 #gpio-cells = <2>;
 475                 interrupt-controller;
 476                 #interrupt-cells = <2>;
 477                 little-endian;
 478         };
 479
 480         sata: sata@3200000 {
 481                 compatible = "fsl,ls1028a-ahci";
 482                 reg = <0x0 0x3200000 0x0 0x10000        /* ccsr sata base */
 483                        0x7 0x100520  0x0 0x4>;          /* ecc sata addr*/
 484                 reg-names = "sata-base", "ecc-addr";
 485                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 486                 status = "disabled";
 487         };
 488
 489         cluster1_core0_watchdog: wdt@c000000 {
 490                 compatible = "arm,sp805-wdt";
 491                 reg = <0x0 0xc000000 0x0 0x1000>;
 492         };
 493 };