1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * NXP ls1028a SOC common device tree source
10 compatible = "fsl,ls1028a";
11 interrupt-parent = <&gic>;
16 compatible = "fixed-clock";
18 clock-frequency = <100000000>;
19 clock-output-names = "sysclk";
22 clockgen: clocking@1300000 {
23 compatible = "fsl,ls1028a-clockgen";
24 reg = <0x0 0x1300000 0x0 0xa0000>;
30 device_type = "memory";
31 reg = <0x00000000 0x01080000 0 0x80000000>;
32 /* DRAM space - 1, size : 2 GB DRAM */
35 gic: interrupt-controller@6000000 {
36 compatible = "arm,gic-v3";
37 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
38 <0x0 0x06040000 0 0x40000>;
39 #interrupt-cells = <3>;
41 interrupts = <1 9 0x4>;
45 compatible = "arm,armv8-timer";
46 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
47 <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
48 <1 11 0x8>, /* Virtual PPI, active-low */
49 <1 10 0x8>; /* Hypervisor PPI, active-low */
52 fspi: flexspi@20C0000 {
53 compatible = "nxp,dn-fspi";
56 reg = <0x0 0x20C0000 0x0 0x10000>,
57 <0x0 0x20000000 0x0 0x10000000>; /*64MB flash*/
58 reg-names = "FSPI", "FSPI-memory";
63 serial0: serial@21c0500 {
64 device_type = "serial";
65 compatible = "fsl,ns16550", "ns16550a";
66 reg = <0x0 0x21c0500 0x0 0x100>;
67 interrupts = <0 32 0x1>; /* edge triggered */
71 serial1: serial@21c0600 {
72 device_type = "serial";
73 compatible = "fsl,ns16550", "ns16550a";
74 reg = <0x0 0x21c0600 0x0 0x100>;
75 interrupts = <0 32 0x1>; /* edge triggered */
80 compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
81 reg = <0x00 0x03400000 0x0 0x80000
82 0x00 0x03480000 0x0 0x40000 /* lut registers */
83 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
84 0x80 0x00000000 0x0 0x20000>; /* configuration space */
85 reg-names = "dbi", "lut", "ctrl", "config";
90 bus-range = <0x0 0xff>;
91 ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */
92 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
96 compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
97 reg = <0x00 0x03500000 0x0 0x80000
98 0x00 0x03580000 0x0 0x40000 /* lut registers */
99 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
100 0x88 0x00000000 0x0 0x20000>; /* configuration space */
101 reg-names = "dbi", "lut", "ctrl", "config";
102 #address-cells = <3>;
106 bus-range = <0x0 0xff>;
107 ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */
108 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
112 compatible = "fsl,vf610-i2c";
113 #address-cells = <1>;
115 reg = <0x0 0x2000000 0x0 0x10000>;
116 interrupts = <0 34 0x4>;
118 clocks = <&clockgen 4 0>;
123 compatible = "fsl,vf610-i2c";
124 #address-cells = <1>;
126 reg = <0x0 0x2010000 0x0 0x10000>;
127 interrupts = <0 34 0x4>;
129 clocks = <&clockgen 4 0>;
134 compatible = "fsl,vf610-i2c";
135 #address-cells = <1>;
137 reg = <0x0 0x2020000 0x0 0x10000>;
138 interrupts = <0 35 0x4>;
140 clocks = <&clockgen 4 0>;
145 compatible = "fsl,vf610-i2c";
146 #address-cells = <1>;
148 reg = <0x0 0x2030000 0x0 0x10000>;
149 interrupts = <0 35 0x4>;
151 clocks = <&clockgen 4 0>;
156 compatible = "fsl,vf610-i2c";
157 #address-cells = <1>;
159 reg = <0x0 0x2040000 0x0 0x10000>;
160 interrupts = <0 74 0x4>;
162 clocks = <&clockgen 4 0>;
167 compatible = "fsl,vf610-i2c";
168 #address-cells = <1>;
170 reg = <0x0 0x2050000 0x0 0x10000>;
171 interrupts = <0 74 0x4>;
173 clocks = <&clockgen 4 0>;
178 compatible = "fsl,vf610-i2c";
179 #address-cells = <1>;
181 reg = <0x0 0x2060000 0x0 0x10000>;
182 interrupts = <0 75 0x4>;
184 clocks = <&clockgen 4 0>;
189 compatible = "fsl,vf610-i2c";
190 #address-cells = <1>;
192 reg = <0x0 0x2070000 0x0 0x10000>;
193 interrupts = <0 75 0x4>;
195 clocks = <&clockgen 4 0>;
200 compatible = "fsl,layerscape-dwc3";
201 reg = <0x0 0x3100000 0x0 0x10000>;
202 interrupts = <0 80 0x4>;
208 compatible = "fsl,layerscape-dwc3";
209 reg = <0x0 0x3110000 0x0 0x10000>;
210 interrupts = <0 81 0x4>;
215 dspi0: dspi@2100000 {
216 compatible = "fsl,vf610-dspi";
217 #address-cells = <1>;
219 reg = <0x0 0x2100000 0x0 0x10000>;
220 interrupts = <0 26 0x4>;
221 clock-names = "dspi";
222 clocks = <&clockgen 4 0>;
228 dspi1: dspi@2110000 {
229 compatible = "fsl,vf610-dspi";
230 #address-cells = <1>;
232 reg = <0x0 0x2110000 0x0 0x10000>;
233 interrupts = <0 26 0x4>;
234 clock-names = "dspi";
235 clocks = <&clockgen 4 0>;
241 dspi2: dspi@2120000 {
242 compatible = "fsl,vf610-dspi";
243 #address-cells = <1>;
245 reg = <0x0 0x2120000 0x0 0x10000>;
246 interrupts = <0 26 0x4>;
247 clock-names = "dspi";
248 clocks = <&clockgen 4 0>;
254 esdhc0: esdhc@2140000 {
255 compatible = "fsl,esdhc";
256 reg = <0x0 0x2140000 0x0 0x10000>;
257 interrupts = <0 28 0x4>;
263 esdhc1: esdhc@2150000 {
264 compatible = "fsl,esdhc";
265 reg = <0x0 0x2150000 0x0 0x10000>;
266 interrupts = <0 63 0x4>;
274 compatible = "fsl,ls1028a-ahci";
275 reg = <0x0 0x3200000 0x0 0x10000>;
276 interrupts = <0 133 4>;
277 clocks = <&clockgen 4 1>;