arch/arm/dts/fsl-ls1028a-qds.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * NXP ls1028AQDS device tree source
   4  *
   5  * Copyright 2019 NXP
   6  *
   7  */
   8
   9 /dts-v1/;
  10
  11 #include "fsl-ls1028a.dtsi"
  12
  13 / {
  14         model = "NXP Layerscape 1028a QDS Board";
  15         compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
  16         aliases {
  17                 spi0 = &fspi;
  18                 spi1 = &dspi0;
  19                 spi2 = &dspi1;
  20                 spi3 = &dspi2;
  21         };
  22
  23 };
  24
  25 &dspi0 {
  26         bus-num = <0>;
  27         status = "okay";
  28
  29         dflash0: sst25wf040b {
  30                 #address-cells = <1>;
  31                 #size-cells = <1>;
  32                 compatible = "spi-flash";
  33                 spi-max-frequency = <3000000>;
  34                 spi-cpol;
  35                 spi-cpha;
  36                 reg = <0>;
  37         };
  38
  39         dflash1: en25s64 {
  40                 #address-cells = <1>;
  41                 #size-cells = <1>;
  42                 compatible = "spi-flash";
  43                 spi-max-frequency = <3000000>;
  44                 spi-cpol;
  45                 spi-cpha;
  46                 reg = <1>;
  47         };
  48         dflash2: n25q128a {
  49                 #address-cells = <1>;
  50                 #size-cells = <1>;
  51                 compatible = "spi-flash";
  52                 spi-max-frequency = <3000000>;
  53                 spi-cpol;
  54                 spi-cpha;
  55                 reg = <2>;
  56         };
  57 };
  58
  59 &dspi1 {
  60         bus-num = <0>;
  61         status = "okay";
  62
  63         dflash3: sst25wf040b {
  64                 #address-cells = <1>;
  65                 #size-cells = <1>;
  66                 compatible = "spi-flash";
  67                 spi-max-frequency = <3000000>;
  68                 spi-cpol;
  69                 spi-cpha;
  70                 reg = <0>;
  71         };
  72
  73         dflash4: en25s64 {
  74                 #address-cells = <1>;
  75                 #size-cells = <1>;
  76                 compatible = "spi-flash";
  77                 spi-max-frequency = <3000000>;
  78                 spi-cpol;
  79                 spi-cpha;
  80                 reg = <1>;
  81         };
  82         dflash5: n25q128a {
  83                 #address-cells = <1>;
  84                 #size-cells = <1>;
  85                 compatible = "spi-flash";
  86                 spi-max-frequency = <3000000>;
  87                 spi-cpol;
  88                 spi-cpha;
  89                 reg = <2>;
  90         };
  91 };
  92
  93 &dspi2 {
  94         bus-num = <0>;
  95         status = "okay";
  96
  97         dflash8: en25s64 {
  98                 #address-cells = <1>;
  99                 #size-cells = <1>;
 100                 compatible = "spi-flash";
 101                 spi-max-frequency = <3000000>;
 102                 spi-cpol;
 103                 spi-cpha;
 104                 reg = <0>;
 105         };
 106 };
 107
 108 &esdhc {
 109         status = "okay";
 110 };
 111
 112 &esdhc1 {
 113         status = "okay";
 114
 115 };
 116
 117 &fspi {
 118         status = "okay";
 119
 120         mt35xu02g0: flash@0 {
 121                 #address-cells = <1>;
 122                 #size-cells = <1>;
 123                 compatible = "jedec,spi-nor";
 124                 spi-max-frequency = <50000000>;
 125                 reg = <0>;
 126                 spi-rx-bus-width = <8>;
 127                 spi-tx-bus-width = <1>;
 128         };
 129 };
 130
 131 &i2c0 {
 132         status = "okay";
 133
 134         fpga@66 {
 135                 #address-cells = <1>;
 136                 #size-cells = <0>;
 137                 compatible = "simple-mfd";
 138                 reg = <0x66>;
 139
 140                 mux-mdio@54 {
 141                         #address-cells = <1>;
 142                         #size-cells = <0>;
 143                         compatible = "mdio-mux-i2creg";
 144                         reg = <0x54>;
 145                         #mux-control-cells = <1>;
 146                         mux-reg-masks = <0x54 0xf0>;
 147                         mdio-parent-bus = <&enetc_mdio_pf3>;
 148
 149                         /* on-board MDIO with a single RGMII PHY */
 150                         mdio@00 {
 151                                 #address-cells = <1>;
 152                                 #size-cells = <0>;
 153                                 reg = <0x00>;
 154
 155                                 qds_phy0: phy@5 {
 156                                         reg = <5>;
 157                                 };
 158                         };
 159                         /* slot 1 */
 160                         slot1: mdio@40 {
 161                                 #address-cells = <1>;
 162                                 #size-cells = <0>;
 163                                 reg = <0x40>;
 164                         };
 165                         /* slot 2 */
 166                         slot2: mdio@50 {
 167                                 #address-cells = <1>;
 168                                 #size-cells = <0>;
 169                                 reg = <0x50>;
 170                         };
 171                         /* slot 3 */
 172                         slot3: mdio@60 {
 173                                 #address-cells = <1>;
 174                                 #size-cells = <0>;
 175                                 reg = <0x60>;
 176                         };
 177                         /* slot 4 */
 178                         slot4: mdio@70 {
 179                                 #address-cells = <1>;
 180                                 #size-cells = <0>;
 181                                 reg = <0x70>;
 182                         };
 183                 };
 184         };
 185
 186         i2c-mux@77 {
 187                 compatible = "nxp,pca9547";
 188                 reg = <0x77>;
 189                 #address-cells = <1>;
 190                 #size-cells = <0>;
 191         };
 192 };
 193
 194 &i2c1 {
 195         status = "okay";
 196
 197         rtc@51 {
 198                 compatible = "nxp,pcf2129";
 199                 reg = <0x51>;
 200         };
 201 };
 202
 203 &i2c2 {
 204         status = "okay";
 205 };
 206
 207 &i2c3 {
 208         status = "okay";
 209 };
 210
 211 &i2c4 {
 212         status = "okay";
 213 };
 214
 215 &i2c5 {
 216         status = "okay";
 217 };
 218
 219 &i2c6 {
 220         status = "okay";
 221 };
 222
 223 &i2c7 {
 224         status = "okay";
 225 };
 226
 227 &lpuart0 {
 228         status = "okay";
 229 };
 230
 231 &sata {
 232         status = "okay";
 233 };
 234
 235 &duart0 {
 236         status = "okay";
 237 };
 238
 239 &duart1 {
 240         status = "okay";
 241 };
 242
 243 &pcie1 {
 244         status = "okay";
 245 };
 246
 247 &pcie2 {
 248         status = "okay";
 249 };
 250
 251 &usb0 {
 252         status = "okay";
 253 };
 254
 255 &usb1 {
 256         status = "okay";
 257 };
 258
 259 &enetc_port1 {
 260         status = "okay";
 261         phy-mode = "rgmii-id";
 262         phy-handle = <&qds_phy0>;
 263 };
 264
 265 &enetc_mdio_pf3 {
 266         status = "okay";
 267 };
 268
 269 #include "fsl-ls1028a-qds-8xxx-sch-24801.dtsi"
 270 #include "fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi"