1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * NXP ls1028AQDS device tree source
11 #include "fsl-ls1028a.dtsi"
14 model = "NXP Layerscape 1028a QDS Board";
15 compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
29 dflash0: sst25wf040b {
32 compatible = "spi-flash";
33 spi-max-frequency = <3000000>;
42 compatible = "spi-flash";
43 spi-max-frequency = <3000000>;
51 compatible = "spi-flash";
52 spi-max-frequency = <3000000>;
63 dflash3: sst25wf040b {
66 compatible = "spi-flash";
67 spi-max-frequency = <3000000>;
76 compatible = "spi-flash";
77 spi-max-frequency = <3000000>;
85 compatible = "spi-flash";
86 spi-max-frequency = <3000000>;
100 compatible = "spi-flash";
101 spi-max-frequency = <3000000>;
120 mt35xu02g0: flash@0 {
121 #address-cells = <1>;
123 compatible = "jedec,spi-nor";
124 spi-max-frequency = <50000000>;
126 spi-rx-bus-width = <8>;
127 spi-tx-bus-width = <1>;
136 #address-cells = <1>;
138 compatible = "simple-mfd";
142 #address-cells = <1>;
144 compatible = "mdio-mux-i2creg";
146 #mux-control-cells = <1>;
147 mux-reg-masks = <0x54 0xf0>;
148 mdio-parent-bus = <&mdio0>;
150 /* on-board MDIO with a single RGMII PHY */
152 #address-cells = <1>;
162 #address-cells = <1>;
168 #address-cells = <1>;
174 #address-cells = <1>;
180 #address-cells = <1>;
188 compatible = "nxp,pca9547";
190 #address-cells = <1>;
199 compatible = "pcf2127-rtc";
255 phy-handle = <&qds_phy0>;
262 #include "fsl-ls1028a-qds-8xxx-sch-24801.dtsi"
263 #include "fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi"