arch/arm/dts/fsl-imx8qxp-apalis.dts

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 /*
   3  * Copyright 2020 Toradex
   4  */
   5
   6 /dts-v1/;
   7
   8 #include "fsl-imx8qxp.dtsi"
   9 #include "fsl-imx8qxp-apalis-u-boot.dtsi"
  10
  11 / {
  12         model = "Toradex Apalis iMX8X";
  13         compatible = "toradex,apalis-imx8x", "fsl,imx8qxp";
  14
  15         chosen {
  16                 bootargs = "console=ttyLP1,115200";
  17                 stdout-path = &lpuart1;
  18         };
  19
  20         regulators {
  21                 compatible = "simple-bus";
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 reg_usb_otg1_vbus: regulator@0 {
  26                         compatible = "regulator-fixed";
  27                         reg = <0>;
  28                         regulator-name = "usb_otg1_vbus";
  29                         regulator-min-microvolt = <5000000>;
  30                         regulator-max-microvolt = <5000000>;
  31                         gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
  32                         enable-active-high;
  33                 };
  34         };
  35 };
  36
  37 &iomuxc {
  38         pinctrl-names = "default";
  39         pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_reset_moci>;
  40
  41         apalis-imx8x {
  42                 /* Apalis UART1 */
  43                 pinctrl_lpuart1: lpuart1grp {
  44                         fsl,pins = <
  45                                 SC_P_UART1_RX_ADMA_UART1_RX             0x06000020      /* SODIMM 118 */
  46                                 SC_P_UART1_TX_ADMA_UART1_TX             0x06000020      /* SODIMM 112 */
  47                         >;
  48                 };
  49
  50                 /* On-module Gigabit Ethernet PHY Micrel KSZ9031 */
  51                 pinctrl_fec1: fec1grp {
  52                         fsl,pins = <
  53                                 SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD      0x14a0
  54                                 SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD      0x14a0
  55                                 SC_P_ENET0_MDC_CONN_ENET0_MDC                   0x06000020
  56                                 SC_P_ENET0_MDIO_CONN_ENET0_MDIO                 0x06000020
  57                                 SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61
  58                                 SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC       0x61
  59                                 SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0     0x61
  60                                 SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1     0x61
  61                                 SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2     0x61
  62                                 SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3     0x61
  63                                 SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC       0x61
  64                                 SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61
  65                                 SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0     0x61
  66                                 SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1     0x61
  67                                 SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2     0x61
  68                                 SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3     0x61
  69                                 /* On-module ETH_RESET# */
  70                                 SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04         0x06000020
  71                                 /* On-module ETH_INT# */
  72                                 SC_P_ADC_IN2_LSIO_GPIO1_IO12                    0x21
  73                         >;
  74                 };
  75
  76                 /* Apalis BKL_ON */
  77                 pinctrl_gpio_bkl_on: gpio-bkl-on {
  78                         fsl,pins = <
  79                                 SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13                 0x40            /* SODIMM 286 */
  80                         >;
  81                 };
  82
  83                 pinctrl_hog0: hog0grp {
  84                         fsl,pins = <
  85                                 SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD          0x000514a0
  86                         >;
  87                 };
  88
  89                 pinctrl_hog1: hog1grp {
  90                         fsl,pins = <
  91                                 /* Apalis USBO1_EN */
  92                                 SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16                0x41            /* SODIMM 274 */
  93                         >;
  94                 };
  95
  96                 /* Apalis RESET_MOCI# */
  97                 pinctrl_reset_moci: gpioresetmocigrp {
  98                         fsl,pins = <
  99                                 SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01        0x21
 100                         >;
 101                 };
 102
 103                 /* On-module eMMC */
 104                 pinctrl_usdhc1: usdhc1grp {
 105                         fsl,pins = <
 106                                 SC_P_EMMC0_CLK_CONN_EMMC0_CLK                   0x06000041
 107                                 SC_P_EMMC0_CMD_CONN_EMMC0_CMD                   0x21
 108                                 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0               0x21
 109                                 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1               0x21
 110                                 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2               0x21
 111                                 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3               0x21
 112                                 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4               0x21
 113                                 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5               0x21
 114                                 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6               0x21
 115                                 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7               0x21
 116                                 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE             0x41
 117                                 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B           0x21
 118                         >;
 119                 };
 120
 121                 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
 122                         fsl,pins = <
 123                                 SC_P_EMMC0_CLK_CONN_EMMC0_CLK                   0x06000041
 124                                 SC_P_EMMC0_CMD_CONN_EMMC0_CMD                   0x21
 125                                 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0               0x21
 126                                 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1               0x21
 127                                 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2               0x21
 128                                 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3               0x21
 129                                 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4               0x21
 130                                 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5               0x21
 131                                 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6               0x21
 132                                 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7               0x21
 133                                 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE             0x41
 134                                 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B           0x21
 135                         >;
 136                 };
 137
 138                 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 139                         fsl,pins = <
 140                                 SC_P_EMMC0_CLK_CONN_EMMC0_CLK                   0x06000041
 141                                 SC_P_EMMC0_CMD_CONN_EMMC0_CMD                   0x21
 142                                 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0               0x21
 143                                 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1               0x21
 144                                 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2               0x21
 145                                 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3               0x21
 146                                 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4               0x21
 147                                 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5               0x21
 148                                 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6               0x21
 149                                 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7               0x21
 150                                 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE             0x41
 151                                 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B           0x21
 152                         >;
 153                 };
 154
 155                 /* Apalis MMC1_CD# */
 156                 pinctrl_usdhc2_gpio: mmc1gpiogrp {
 157                         fsl,pins = <
 158                                 SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22                0x06000021      /* SODIMM 164 */
 159                         >;
 160                 };
 161
 162                 pinctrl_usdhc2_gpio_sleep: usdhc1gpioslpgrp {
 163                         fsl,pins = <
 164                                 SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22                0x60            /* SODIMM 164 */
 165                         >;
 166                 };
 167
 168                 /* Apalis USBH_EN */
 169                 pinctrl_usbh_en: usbhen {
 170                         fsl,pins = <
 171                                 SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04                0x40            /* SODIMM 84 */
 172                         >;
 173                 };
 174
 175                 /* Apalis MMC1 */
 176                 pinctrl_usdhc2: usdhc2grp {
 177                         fsl,pins = <
 178                                 SC_P_USDHC1_CLK_CONN_USDHC1_CLK                 0x06000041      /* SODIMM 154 */
 179                                 SC_P_USDHC1_CMD_CONN_USDHC1_CMD                 0x21            /* SODIMM 150 */
 180                                 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0             0x21            /* SODIMM 160 */
 181                                 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1             0x21            /* SODIMM 162 */
 182                                 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2             0x21            /* SODIMM 144 */
 183                                 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3             0x21            /* SODIMM 146 */
 184                                 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT         0x21
 185                         >;
 186                 };
 187
 188                 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
 189                         fsl,pins = <
 190                                 SC_P_USDHC1_CLK_CONN_USDHC1_CLK                 0x06000041      /* SODIMM 154 */
 191                                 SC_P_USDHC1_CMD_CONN_USDHC1_CMD                 0x21            /* SODIMM 150 */
 192                                 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0             0x21            /* SODIMM 160 */
 193                                 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1             0x21            /* SODIMM 162 */
 194                                 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2             0x21            /* SODIMM 144 */
 195                                 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3             0x21            /* SODIMM 146 */
 196                                 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT         0x21
 197                         >;
 198                 };
 199
 200                 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
 201                         fsl,pins = <
 202                                 SC_P_USDHC1_CLK_CONN_USDHC1_CLK                 0x06000041      /* SODIMM 154 */
 203                                 SC_P_USDHC1_CMD_CONN_USDHC1_CMD                 0x21            /* SODIMM 150 */
 204                                 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0             0x21            /* SODIMM 160 */
 205                                 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1             0x21            /* SODIMM 162 */
 206                                 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2             0x21            /* SODIMM 144 */
 207                                 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3             0x21            /* SODIMM 146 */
 208                                 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT         0x21
 209                         >;
 210                 };
 211
 212                 pinctrl_usdhc2_sleep: usdhc2slpgrp {
 213                         fsl,pins = <
 214                                 SC_P_USDHC1_CLK_LSIO_GPIO4_IO23                 0x60            /* SODIMM 154 */
 215                                 SC_P_USDHC1_CMD_LSIO_GPIO4_IO24                 0x60            /* SODIMM 150 */
 216                                 SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25               0x60            /* SODIMM 160 */
 217                                 SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26               0x60            /* SODIMM 162 */
 218                                 SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27               0x60            /* SODIMM 144 */
 219                                 SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28               0x60            /* SODIMM 146 */
 220                                 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT         0x21
 221                         >;
 222                 };
 223         };
 224 };
 225
 226 /* Apalis Gigabit LAN */
 227 &fec1 {
 228         pinctrl-names = "default";
 229         pinctrl-0 = <&pinctrl_fec1>;
 230         fsl,magic-packet;
 231         phy-handle = <&ethphy0>;
 232         phy-mode = "rgmii";
 233         phy-reset-duration = <10>;
 234         phy-reset-post-delay = <150>;
 235         phy-reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
 236         status = "okay";
 237
 238         mdio {
 239                 #address-cells = <1>;
 240                 #size-cells = <0>;
 241
 242                 ethphy0: ethernet-phy@4 {
 243                         compatible = "ethernet-phy-ieee802.3-c22";
 244                         reg = <4>;
 245                 };
 246         };
 247 };
 248
 249 /* Apalis UART1 */
 250 &lpuart1 {
 251         pinctrl-names = "default";
 252         pinctrl-0 = <&pinctrl_lpuart1>;
 253         status = "okay";
 254 };
 255
 256 /* On-module eMMC */
 257 &usdhc1 {
 258         bus-width = <8>;
 259         non-removable;
 260         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 261         pinctrl-0 = <&pinctrl_usdhc1>;
 262         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 263         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 264         status = "okay";
 265 };
 266
 267 /* Apalis MMC1 */
 268 &usdhc2 {
 269         bus-width = <4>;
 270         cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
 271         pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
 272         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 273         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 274         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 275         pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
 276         disable-wp;
 277         status = "okay";
 278 };