arch/arm/dts/fsl-imx8mq.dtsi

   1 /*
   2  * Copyright (C) 2016 Freescale Semiconductor, Inc.
   3  * Copyright 2017 NXP
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include "fsl-imx8-ca53.dtsi"
  17 #include <dt-bindings/clock/imx8mq-clock.h>
  18 #include <dt-bindings/gpio/gpio.h>
  19 #include <dt-bindings/input/input.h>
  20 #include <dt-bindings/interrupt-controller/arm-gic.h>
  21 #include <dt-bindings/pinctrl/pins-imx8mq.h>
  22 #include <dt-bindings/power/imx8mq-power.h>
  23 #include <dt-bindings/thermal/thermal.h>
  24
  25 / {
  26         compatible = "fsl,imx8mq";
  27         interrupt-parent = <&gpc>;
  28         #address-cells = <2>;
  29         #size-cells = <2>;
  30
  31         aliases {
  32                 ethernet0 = &fec1;
  33                 mmc0 = &usdhc1;
  34                 mmc1 = &usdhc2;
  35                 gpio0 = &gpio1;
  36                 gpio1 = &gpio2;
  37                 gpio2 = &gpio3;
  38                 gpio3 = &gpio4;
  39                 gpio4 = &gpio5;
  40                 i2c0 = &i2c1;
  41                 i2c1 = &i2c2;
  42                 i2c2 = &i2c3;
  43                 i2c3 = &i2c4;
  44         };
  45
  46         memory@40000000 {
  47                 device_type = "memory";
  48                 reg = <0x00000000 0x40000000 0 0xc0000000>;
  49         };
  50
  51         gic: interrupt-controller@38800000 {
  52                 compatible = "arm,gic-v3";
  53                 reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
  54                       <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
  55                 #interrupt-cells = <3>;
  56                 interrupt-controller;
  57                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  58                 interrupt-parent = <&gic>;
  59         };
  60
  61         timer {
  62                 compatible = "arm,armv8-timer";
  63                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) |
  64                              IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
  65                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) |
  66                              IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
  67                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) |
  68                              IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
  69                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) |
  70                              IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
  71                 clock-frequency = <8333333>;
  72                 interrupt-parent = <&gic>;
  73         };
  74
  75         pwm2: pwm@30670000 {
  76                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
  77                 reg = <0x0 0x30670000 0x0 0x10000>;
  78                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
  79                 clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
  80                          <&clk IMX8MQ_CLK_PWM2_ROOT>;
  81                 clock-names = "ipg", "per";
  82                 #pwm-cells = <2>;
  83                 status = "disabled";
  84         };
  85
  86         gpio1: gpio@30200000 {
  87                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
  88                 reg = <0x0 0x30200000 0x0 0x10000>;
  89                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
  90                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  91                 gpio-controller;
  92                 #gpio-cells = <2>;
  93                 interrupt-controller;
  94                 #interrupt-cells = <2>;
  95         };
  96
  97         gpio2: gpio@30210000 {
  98                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
  99                 reg = <0x0 0x30210000 0x0 0x10000>;
 100                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 101                         <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 102                 gpio-controller;
 103                 #gpio-cells = <2>;
 104                 interrupt-controller;
 105                 #interrupt-cells = <2>;
 106         };
 107
 108         gpio3: gpio@30220000 {
 109                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 110                 reg = <0x0 0x30220000 0x0 0x10000>;
 111                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 112                         <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 113                 gpio-controller;
 114                 #gpio-cells = <2>;
 115                 interrupt-controller;
 116                 #interrupt-cells = <2>;
 117         };
 118
 119         gpio4: gpio@30230000 {
 120                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 121                 reg = <0x0 0x30230000 0x0 0x10000>;
 122                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 123                                 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 124                 gpio-controller;
 125                 #gpio-cells = <2>;
 126                 interrupt-controller;
 127                 #interrupt-cells = <2>;
 128         };
 129
 130         gpio5: gpio@30240000 {
 131                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 132                 reg = <0x0 0x30240000 0x0 0x10000>;
 133                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 134                         <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 135                 gpio-controller;
 136                 #gpio-cells = <2>;
 137                 interrupt-controller;
 138                 #interrupt-cells = <2>;
 139         };
 140
 141         tmu: tmu@30260000 {
 142                 compatible = "fsl,imx8mq-tmu";
 143                 reg = <0x0 0x30260000 0x0 0x10000>;
 144                 interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 145                 little-endian;
 146                 u-boot,dm-pre-reloc;
 147                 fsl,tmu-range = <0xa0000 0x90026 0x8004a 0x1006a>;
 148                 fsl,tmu-calibration = <0x00000000 0x00000020
 149                                        0x00000001 0x00000028
 150                                        0x00000002 0x00000030
 151                                        0x00000003 0x00000038
 152                                        0x00000004 0x00000040
 153                                        0x00000005 0x00000048
 154                                        0x00000006 0x00000050
 155                                        0x00000007 0x00000058
 156                                        0x00000008 0x00000060
 157                                        0x00000009 0x00000068
 158                                        0x0000000a 0x00000070
 159                                        0x0000000b 0x00000077
 160
 161                                        0x00010000 0x00000057
 162                                        0x00010001 0x0000005b
 163                                        0x00010002 0x0000005f
 164                                        0x00010003 0x00000063
 165                                        0x00010004 0x00000067
 166                                        0x00010005 0x0000006b
 167                                        0x00010006 0x0000006f
 168                                        0x00010007 0x00000073
 169                                        0x00010008 0x00000077
 170                                        0x00010009 0x0000007b
 171                                        0x0001000a 0x0000007f
 172
 173                                        0x00020000 0x00000002
 174                                        0x00020001 0x0000000e
 175                                        0x00020002 0x0000001a
 176                                        0x00020003 0x00000026
 177                                        0x00020004 0x00000032
 178                                        0x00020005 0x0000003e
 179                                        0x00020006 0x0000004a
 180                                        0x00020007 0x00000056
 181                                        0x00020008 0x00000062
 182
 183                                        0x00030000 0x00000000
 184                                        0x00030001 0x00000008
 185                                        0x00030002 0x00000010
 186                                        0x00030003 0x00000018
 187                                        0x00030004 0x00000020
 188                                        0x00030005 0x00000028
 189                                        0x00030006 0x00000030
 190                                        0x00030007 0x00000038>;
 191                 #thermal-sensor-cells =  <0>;
 192         };
 193
 194         thermal-zones {
 195                 /* cpu thermal */
 196                 cpu-thermal {
 197                         polling-delay-passive = <250>;
 198                         polling-delay = <2000>;
 199                         thermal-sensors = <&tmu>;
 200                         trips {
 201                                 cpu_alert0: trip0 {
 202                                         temperature = <85000>;
 203                                         hysteresis = <2000>;
 204                                         type = "passive";
 205                                 };
 206                                 cpu_crit0: trip1 {
 207                                         temperature = <125000>;
 208                                         hysteresis = <2000>;
 209                                         type = "critical";
 210                                 };
 211                         };
 212
 213                         cooling-maps {
 214                                 map0 {
 215                                         trip = <&cpu_alert0>;
 216                                         cooling-device =
 217                                         <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 218                                 };
 219                         };
 220                 };
 221         };
 222
 223         lcdif: lcdif@30320000 {
 224                 compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
 225                 reg = <0x0 0x30320000 0x0 0x10000>;
 226                 clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_DIV>,
 227                          <&clk IMX8MQ_CLK_DUMMY>,
 228                          <&clk IMX8MQ_CLK_DUMMY>;
 229                 clock-names = "pix", "axi", "disp_axi";
 230                 assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_SRC>;
 231                 assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
 232                 assigned-clock-rate = <594000000>;
 233                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 234                 status = "disabled";
 235         };
 236
 237         iomuxc: iomuxc@30330000 {
 238                 compatible = "fsl,imx8mq-iomuxc";
 239                 reg = <0x0 0x30330000 0x0 0x10000>;
 240         };
 241
 242         gpr: iomuxc-gpr@30340000 {
 243                 compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx7d-iomuxc-gpr", "syscon";
 244                 reg = <0x0 0x30340000 0x0 0x10000>;
 245         };
 246
 247         ocotp: ocotp-ctrl@30350000 {
 248                 compatible = "fsl,imx8mq-ocotp", "fsl,imx7d-ocotp", "syscon";
 249                 reg = <0x0 0x30350000 0x0 0x10000>;
 250         };
 251
 252         anatop: anatop@30360000 {
 253                 compatible = "fsl,imx8mq-anatop", "fsl,imx6q-anatop",
 254                         "syscon", "simple-bus";
 255                 reg = <0x0 0x30360000 0x0 0x10000>;
 256                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 257         };
 258
 259         clk: ccm@30380000 {
 260                 compatible = "fsl,imx8mq-ccm";
 261                 reg = <0x0 0x30380000 0x0 0x10000>;
 262                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 263                         <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 264                 #clock-cells = <1>;
 265         };
 266
 267         gpc: gpc@303a0000 {
 268                 compatible = "fsl,imx8mq-gpc", "fsl,imx7d-gpc", "syscon";
 269                 reg = <0x0 0x303a0000 0x0 0x10000>;
 270                 interrupt-controller;
 271                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 272                 #interrupt-cells = <3>;
 273                 interrupt-parent = <&gic>;
 274
 275                 pgc {
 276                         #address-cells = <1>;
 277                         #size-cells = <0>;
 278
 279                         /*
 280                          * As per comment in ATF source code:
 281                          *
 282                          * PCIE1 and PCIE2 share the
 283                          * same reset signal, if we
 284                          * power down PCIE2, PCIE1
 285                          * will be held in reset too.
 286                          *
 287                          * So instead of creating two
 288                          * separate power domains for
 289                          * PCIE1 and PCIE2 we create a
 290                          * link between both and use
 291                          * it as a shared PCIE power
 292                          * domain.
 293                          */
 294                         pgc_pcie: power-domain@1 {
 295                                 #power-domain-cells = <0>;
 296                                 reg = <IMX8M_POWER_DOMAIN_PCIE1>;
 297                                 power-domains = <&pgc_pcie2>;
 298                         };
 299
 300                         pgc_pcie2: power-domain@a {
 301                                 #power-domain-cells = <0>;
 302                                 reg = <IMX8M_POWER_DOMAIN_PCIE2>;
 303                         };
 304                 };
 305         };
 306
 307         usdhc1: usdhc@30b40000 {
 308                 compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
 309                 reg = <0x0 0x30b40000 0x0 0x10000>;
 310                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 311                 clocks = <&clk IMX8MQ_CLK_DUMMY>,
 312                         <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
 313                         <&clk IMX8MQ_CLK_USDHC1_ROOT>;
 314                 clock-names = "ipg", "ahb", "per";
 315                 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1_DIV>;
 316                 assigned-clock-rates = <400000000>;
 317                 fsl,tuning-start-tap = <20>;
 318                 fsl,tuning-step= <2>;
 319                 bus-width = <4>;
 320                 status = "disabled";
 321         };
 322
 323         usdhc2: usdhc@30b50000 {
 324                 compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
 325                 reg = <0x0 0x30b50000 0x0 0x10000>;
 326                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 327                 clocks = <&clk IMX8MQ_CLK_DUMMY>,
 328                         <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
 329                         <&clk IMX8MQ_CLK_USDHC2_ROOT>;
 330                 clock-names = "ipg", "ahb", "per";
 331                 fsl,tuning-start-tap = <20>;
 332                 fsl,tuning-step= <2>;
 333                 bus-width = <4>;
 334                 status = "disabled";
 335         };
 336
 337         fec1: ethernet@30be0000 {
 338                 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
 339                 reg = <0x0 0x30be0000 0x0 0x10000>;
 340                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 341                         <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 342                         <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 343                 clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
 344                         <&clk IMX8MQ_CLK_ENET1_ROOT>,
 345                         <&clk IMX8MQ_CLK_ENET_TIMER_DIV>,
 346                         <&clk IMX8MQ_CLK_ENET_REF_DIV>,
 347                         <&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>;
 348                 clock-names = "ipg", "ahb", "ptp",
 349                         "enet_clk_ref", "enet_out";
 350                 assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI_SRC>,
 351                                   <&clk IMX8MQ_CLK_ENET_TIMER_SRC>,
 352                                   <&clk IMX8MQ_CLK_ENET_REF_SRC>,
 353                                   <&clk IMX8MQ_CLK_ENET_TIMER_DIV>;
 354                 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
 355                                          <&clk IMX8MQ_SYS2_PLL_100M>,
 356                                          <&clk IMX8MQ_SYS2_PLL_125M>;
 357                 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
 358                 stop-mode = <&gpr 0x10 3>;
 359                 fsl,num-tx-queues=<3>;
 360                 fsl,num-rx-queues=<3>;
 361                 fsl,wakeup_irq = <2>;
 362                 status = "disabled";
 363         };
 364
 365         imx_ion {
 366                 compatible = "fsl,mxc-ion";
 367                 fsl,heap-id = <0>;
 368         };
 369
 370         i2c1: i2c@30a20000 {
 371                 #address-cells = <1>;
 372                 #size-cells = <0>;
 373                 compatible = "fsl,imx21-i2c";
 374                 reg = <0x0 0x30a20000 0x0 0x10000>;
 375                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 376                 clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
 377                 status = "disabled";
 378         };
 379
 380         i2c2: i2c@30a30000 {
 381                 #address-cells = <1>;
 382                 #size-cells = <0>;
 383                 compatible = "fsl,imx21-i2c";
 384                 reg = <0x0 0x30a30000 0x0 0x10000>;
 385                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 386                 clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
 387                 status = "disabled";
 388         };
 389
 390         i2c3: i2c@30a40000 {
 391                 #address-cells = <1>;
 392                 #size-cells = <0>;
 393                 compatible = "fsl,imx21-i2c";
 394                 reg = <0x0 0x30a40000 0x0 0x10000>;
 395                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 396                 clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
 397                 status = "disabled";
 398         };
 399
 400         i2c4: i2c@30a50000 {
 401                 #address-cells = <1>;
 402                 #size-cells = <0>;
 403                 compatible = "fsl,imx21-i2c";
 404                 reg = <0x0 0x30a50000 0x0 0x10000>;
 405                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 406                 clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
 407                 status = "disabled";
 408         };
 409
 410         wdog1: wdog@30280000 {
 411                         compatible = "fsl,imx21-wdt";
 412                         reg = <0 0x30280000 0 0x10000>;
 413                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 414                         clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
 415                         status = "disabled";
 416         };
 417
 418         wdog2: wdog@30290000 {
 419                         compatible = "fsl,imx21-wdt";
 420                         reg = <0 0x30290000 0 0x10000>;
 421                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 422                         clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
 423                         status = "disabled";
 424         };
 425
 426         wdog3: wdog@302a0000 {
 427                         compatible = "fsl,imx21-wdt";
 428                         reg = <0 0x302a0000 0 0x10000>;
 429                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 430                         clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
 431                         status = "disabled";
 432         };
 433
 434         dma_cap: dma_cap {
 435                 compatible = "dma-capability";
 436                 only-dma-mask32 = <1>;
 437         };
 438
 439         qspi: qspi@30bb0000 {
 440                 #address-cells = <1>;
 441                 #size-cells = <0>;
 442                 compatible = "fsl,imx7d-qspi";
 443                 reg = <0 0x30bb0000 0 0x10000>, <0 0x08000000 0 0x10000000>;
 444                 reg-names = "QuadSPI", "QuadSPI-memory";
 445                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 446                 clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
 447                 <&clk IMX8MQ_CLK_QSPI_ROOT>;
 448                 clock-names = "qspi_en", "qspi";
 449                 status = "disabled";
 450         };
 451 };
 452
 453 &A53_0 {
 454         #cooling-cells = <2>;
 455 };