arch/arm/dts/fsl-imx8mq.dtsi

   1 /*
   2  * Copyright (C) 2016 Freescale Semiconductor, Inc.
   3  * Copyright 2017 NXP
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include "fsl-imx8-ca53.dtsi"
  17 #include <dt-bindings/clock/imx8mq-clock.h>
  18 #include <dt-bindings/gpio/gpio.h>
  19 #include <dt-bindings/input/input.h>
  20 #include <dt-bindings/interrupt-controller/arm-gic.h>
  21 #include <dt-bindings/pinctrl/pins-imx8mq.h>
  22 #include <dt-bindings/reset/imx8mq-reset.h>
  23 #include <dt-bindings/power/imx8mq-power.h>
  24 #include <dt-bindings/thermal/thermal.h>
  25
  26 / {
  27         compatible = "fsl,imx8mq";
  28         interrupt-parent = <&gpc>;
  29         #address-cells = <2>;
  30         #size-cells = <2>;
  31
  32         aliases {
  33                 ethernet0 = &fec1;
  34                 mmc0 = &usdhc1;
  35                 mmc1 = &usdhc2;
  36                 gpio0 = &gpio1;
  37                 gpio1 = &gpio2;
  38                 gpio2 = &gpio3;
  39                 gpio3 = &gpio4;
  40                 gpio4 = &gpio5;
  41                 i2c0 = &i2c1;
  42                 i2c1 = &i2c2;
  43                 i2c2 = &i2c3;
  44                 i2c3 = &i2c4;
  45         };
  46
  47         memory@40000000 {
  48                 device_type = "memory";
  49                 reg = <0x00000000 0x40000000 0 0xc0000000>;
  50         };
  51
  52         gic: interrupt-controller@38800000 {
  53                 compatible = "arm,gic-v3";
  54                 reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
  55                       <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
  56                 #interrupt-cells = <3>;
  57                 interrupt-controller;
  58                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  59                 interrupt-parent = <&gic>;
  60         };
  61
  62         timer {
  63                 compatible = "arm,armv8-timer";
  64                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) |
  65                              IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
  66                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) |
  67                              IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
  68                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) |
  69                              IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
  70                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) |
  71                              IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
  72                 clock-frequency = <8333333>;
  73                 interrupt-parent = <&gic>;
  74         };
  75
  76         pwm2: pwm@30670000 {
  77                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
  78                 reg = <0x0 0x30670000 0x0 0x10000>;
  79                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
  80                 clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
  81                          <&clk IMX8MQ_CLK_PWM2_ROOT>;
  82                 clock-names = "ipg", "per";
  83                 #pwm-cells = <2>;
  84                 status = "disabled";
  85         };
  86
  87         gpio1: gpio@30200000 {
  88                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
  89                 reg = <0x0 0x30200000 0x0 0x10000>;
  90                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
  91                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  92                 gpio-controller;
  93                 #gpio-cells = <2>;
  94                 interrupt-controller;
  95                 #interrupt-cells = <2>;
  96         };
  97
  98         gpio2: gpio@30210000 {
  99                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 100                 reg = <0x0 0x30210000 0x0 0x10000>;
 101                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 102                         <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 103                 gpio-controller;
 104                 #gpio-cells = <2>;
 105                 interrupt-controller;
 106                 #interrupt-cells = <2>;
 107         };
 108
 109         gpio3: gpio@30220000 {
 110                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 111                 reg = <0x0 0x30220000 0x0 0x10000>;
 112                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 113                         <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 114                 gpio-controller;
 115                 #gpio-cells = <2>;
 116                 interrupt-controller;
 117                 #interrupt-cells = <2>;
 118         };
 119
 120         gpio4: gpio@30230000 {
 121                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 122                 reg = <0x0 0x30230000 0x0 0x10000>;
 123                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 124                                 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 125                 gpio-controller;
 126                 #gpio-cells = <2>;
 127                 interrupt-controller;
 128                 #interrupt-cells = <2>;
 129         };
 130
 131         gpio5: gpio@30240000 {
 132                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 133                 reg = <0x0 0x30240000 0x0 0x10000>;
 134                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 135                         <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 136                 gpio-controller;
 137                 #gpio-cells = <2>;
 138                 interrupt-controller;
 139                 #interrupt-cells = <2>;
 140         };
 141
 142         tmu: tmu@30260000 {
 143                 compatible = "fsl,imx8mq-tmu";
 144                 reg = <0x0 0x30260000 0x0 0x10000>;
 145                 interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 146                 little-endian;
 147                 u-boot,dm-pre-reloc;
 148                 fsl,tmu-range = <0xa0000 0x90026 0x8004a 0x1006a>;
 149                 fsl,tmu-calibration = <0x00000000 0x00000020
 150                                        0x00000001 0x00000028
 151                                        0x00000002 0x00000030
 152                                        0x00000003 0x00000038
 153                                        0x00000004 0x00000040
 154                                        0x00000005 0x00000048
 155                                        0x00000006 0x00000050
 156                                        0x00000007 0x00000058
 157                                        0x00000008 0x00000060
 158                                        0x00000009 0x00000068
 159                                        0x0000000a 0x00000070
 160                                        0x0000000b 0x00000077
 161
 162                                        0x00010000 0x00000057
 163                                        0x00010001 0x0000005b
 164                                        0x00010002 0x0000005f
 165                                        0x00010003 0x00000063
 166                                        0x00010004 0x00000067
 167                                        0x00010005 0x0000006b
 168                                        0x00010006 0x0000006f
 169                                        0x00010007 0x00000073
 170                                        0x00010008 0x00000077
 171                                        0x00010009 0x0000007b
 172                                        0x0001000a 0x0000007f
 173
 174                                        0x00020000 0x00000002
 175                                        0x00020001 0x0000000e
 176                                        0x00020002 0x0000001a
 177                                        0x00020003 0x00000026
 178                                        0x00020004 0x00000032
 179                                        0x00020005 0x0000003e
 180                                        0x00020006 0x0000004a
 181                                        0x00020007 0x00000056
 182                                        0x00020008 0x00000062
 183
 184                                        0x00030000 0x00000000
 185                                        0x00030001 0x00000008
 186                                        0x00030002 0x00000010
 187                                        0x00030003 0x00000018
 188                                        0x00030004 0x00000020
 189                                        0x00030005 0x00000028
 190                                        0x00030006 0x00000030
 191                                        0x00030007 0x00000038>;
 192                 #thermal-sensor-cells =  <0>;
 193         };
 194
 195         thermal-zones {
 196                 /* cpu thermal */
 197                 cpu-thermal {
 198                         polling-delay-passive = <250>;
 199                         polling-delay = <2000>;
 200                         thermal-sensors = <&tmu>;
 201                         trips {
 202                                 cpu_alert0: trip0 {
 203                                         temperature = <85000>;
 204                                         hysteresis = <2000>;
 205                                         type = "passive";
 206                                 };
 207                                 cpu_crit0: trip1 {
 208                                         temperature = <125000>;
 209                                         hysteresis = <2000>;
 210                                         type = "critical";
 211                                 };
 212                         };
 213
 214                         cooling-maps {
 215                                 map0 {
 216                                         trip = <&cpu_alert0>;
 217                                         cooling-device =
 218                                         <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 219                                 };
 220                         };
 221                 };
 222         };
 223
 224         lcdif: lcdif@30320000 {
 225                 compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
 226                 reg = <0x0 0x30320000 0x0 0x10000>;
 227                 clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_DIV>,
 228                          <&clk IMX8MQ_CLK_DUMMY>,
 229                          <&clk IMX8MQ_CLK_DUMMY>;
 230                 clock-names = "pix", "axi", "disp_axi";
 231                 assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_SRC>;
 232                 assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
 233                 assigned-clock-rate = <594000000>;
 234                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 235                 status = "disabled";
 236         };
 237
 238         iomuxc: iomuxc@30330000 {
 239                 compatible = "fsl,imx8mq-iomuxc";
 240                 reg = <0x0 0x30330000 0x0 0x10000>;
 241         };
 242
 243         gpr: iomuxc-gpr@30340000 {
 244                 compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx7d-iomuxc-gpr", "syscon";
 245                 reg = <0x0 0x30340000 0x0 0x10000>;
 246         };
 247
 248         ocotp: ocotp-ctrl@30350000 {
 249                 compatible = "fsl,imx8mq-ocotp", "fsl,imx7d-ocotp", "syscon";
 250                 reg = <0x0 0x30350000 0x0 0x10000>;
 251         };
 252
 253         anatop: anatop@30360000 {
 254                 compatible = "fsl,imx8mq-anatop", "fsl,imx6q-anatop",
 255                         "syscon", "simple-bus";
 256                 reg = <0x0 0x30360000 0x0 0x10000>;
 257                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 258         };
 259
 260         clk: ccm@30380000 {
 261                 compatible = "fsl,imx8mq-ccm";
 262                 reg = <0x0 0x30380000 0x0 0x10000>;
 263                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 264                         <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 265                 #clock-cells = <1>;
 266         };
 267
 268         src: reset-controller@30390000 {
 269                 compatible = "fsl,imx8mq-src", "syscon";
 270                 reg = <0x0 0x30390000 0x0 0x10000>;
 271                 #reset-cells = <1>;
 272         };
 273
 274         gpc: gpc@303a0000 {
 275                 compatible = "fsl,imx8mq-gpc", "fsl,imx7d-gpc", "syscon";
 276                 reg = <0x0 0x303a0000 0x0 0x10000>;
 277                 interrupt-controller;
 278                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 279                 #interrupt-cells = <3>;
 280                 interrupt-parent = <&gic>;
 281
 282                 pgc {
 283                         #address-cells = <1>;
 284                         #size-cells = <0>;
 285
 286                         /*
 287                          * As per comment in ATF source code:
 288                          *
 289                          * PCIE1 and PCIE2 share the
 290                          * same reset signal, if we
 291                          * power down PCIE2, PCIE1
 292                          * will be held in reset too.
 293                          *
 294                          * So instead of creating two
 295                          * separate power domains for
 296                          * PCIE1 and PCIE2 we create a
 297                          * link between both and use
 298                          * it as a shared PCIE power
 299                          * domain.
 300                          */
 301                         pgc_pcie: power-domain@1 {
 302                                 #power-domain-cells = <0>;
 303                                 reg = <IMX8M_POWER_DOMAIN_PCIE1>;
 304                                 power-domains = <&pgc_pcie2>;
 305                         };
 306
 307                         pgc_pcie2: power-domain@a {
 308                                 #power-domain-cells = <0>;
 309                                 reg = <IMX8M_POWER_DOMAIN_PCIE2>;
 310                         };
 311                 };
 312         };
 313
 314         usdhc1: usdhc@30b40000 {
 315                 compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
 316                 reg = <0x0 0x30b40000 0x0 0x10000>;
 317                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 318                 clocks = <&clk IMX8MQ_CLK_DUMMY>,
 319                         <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
 320                         <&clk IMX8MQ_CLK_USDHC1_ROOT>;
 321                 clock-names = "ipg", "ahb", "per";
 322                 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1_DIV>;
 323                 assigned-clock-rates = <400000000>;
 324                 fsl,tuning-start-tap = <20>;
 325                 fsl,tuning-step= <2>;
 326                 bus-width = <4>;
 327                 status = "disabled";
 328         };
 329
 330         usdhc2: usdhc@30b50000 {
 331                 compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
 332                 reg = <0x0 0x30b50000 0x0 0x10000>;
 333                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 334                 clocks = <&clk IMX8MQ_CLK_DUMMY>,
 335                         <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
 336                         <&clk IMX8MQ_CLK_USDHC2_ROOT>;
 337                 clock-names = "ipg", "ahb", "per";
 338                 fsl,tuning-start-tap = <20>;
 339                 fsl,tuning-step= <2>;
 340                 bus-width = <4>;
 341                 status = "disabled";
 342         };
 343
 344         fec1: ethernet@30be0000 {
 345                 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
 346                 reg = <0x0 0x30be0000 0x0 0x10000>;
 347                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 348                         <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 349                         <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 350                 clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
 351                         <&clk IMX8MQ_CLK_ENET1_ROOT>,
 352                         <&clk IMX8MQ_CLK_ENET_TIMER_DIV>,
 353                         <&clk IMX8MQ_CLK_ENET_REF_DIV>,
 354                         <&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>;
 355                 clock-names = "ipg", "ahb", "ptp",
 356                         "enet_clk_ref", "enet_out";
 357                 assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI_SRC>,
 358                                   <&clk IMX8MQ_CLK_ENET_TIMER_SRC>,
 359                                   <&clk IMX8MQ_CLK_ENET_REF_SRC>,
 360                                   <&clk IMX8MQ_CLK_ENET_TIMER_DIV>;
 361                 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
 362                                          <&clk IMX8MQ_SYS2_PLL_100M>,
 363                                          <&clk IMX8MQ_SYS2_PLL_125M>;
 364                 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
 365                 stop-mode = <&gpr 0x10 3>;
 366                 fsl,num-tx-queues=<3>;
 367                 fsl,num-rx-queues=<3>;
 368                 fsl,wakeup_irq = <2>;
 369                 status = "disabled";
 370         };
 371
 372         imx_ion {
 373                 compatible = "fsl,mxc-ion";
 374                 fsl,heap-id = <0>;
 375         };
 376
 377         i2c1: i2c@30a20000 {
 378                 #address-cells = <1>;
 379                 #size-cells = <0>;
 380                 compatible = "fsl,imx21-i2c";
 381                 reg = <0x0 0x30a20000 0x0 0x10000>;
 382                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 383                 clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
 384                 status = "disabled";
 385         };
 386
 387         i2c2: i2c@30a30000 {
 388                 #address-cells = <1>;
 389                 #size-cells = <0>;
 390                 compatible = "fsl,imx21-i2c";
 391                 reg = <0x0 0x30a30000 0x0 0x10000>;
 392                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 393                 clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
 394                 status = "disabled";
 395         };
 396
 397         i2c3: i2c@30a40000 {
 398                 #address-cells = <1>;
 399                 #size-cells = <0>;
 400                 compatible = "fsl,imx21-i2c";
 401                 reg = <0x0 0x30a40000 0x0 0x10000>;
 402                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 403                 clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
 404                 status = "disabled";
 405         };
 406
 407         i2c4: i2c@30a50000 {
 408                 #address-cells = <1>;
 409                 #size-cells = <0>;
 410                 compatible = "fsl,imx21-i2c";
 411                 reg = <0x0 0x30a50000 0x0 0x10000>;
 412                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 413                 clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
 414                 status = "disabled";
 415         };
 416
 417         wdog1: wdog@30280000 {
 418                         compatible = "fsl,imx21-wdt";
 419                         reg = <0 0x30280000 0 0x10000>;
 420                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 421                         clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
 422                         status = "disabled";
 423         };
 424
 425         wdog2: wdog@30290000 {
 426                         compatible = "fsl,imx21-wdt";
 427                         reg = <0 0x30290000 0 0x10000>;
 428                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 429                         clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
 430                         status = "disabled";
 431         };
 432
 433         wdog3: wdog@302a0000 {
 434                         compatible = "fsl,imx21-wdt";
 435                         reg = <0 0x302a0000 0 0x10000>;
 436                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 437                         clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
 438                         status = "disabled";
 439         };
 440
 441         dma_cap: dma_cap {
 442                 compatible = "dma-capability";
 443                 only-dma-mask32 = <1>;
 444         };
 445
 446         qspi: qspi@30bb0000 {
 447                 #address-cells = <1>;
 448                 #size-cells = <0>;
 449                 compatible = "fsl,imx7d-qspi";
 450                 reg = <0 0x30bb0000 0 0x10000>, <0 0x08000000 0 0x10000000>;
 451                 reg-names = "QuadSPI", "QuadSPI-memory";
 452                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 453                 clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
 454                 <&clk IMX8MQ_CLK_QSPI_ROOT>;
 455                 clock-names = "qspi_en", "qspi";
 456                 status = "disabled";
 457         };
 458 };
 459
 460 &A53_0 {
 461         #cooling-cells = <2>;
 462 };