1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include "fsl-imx8-ca35.dtsi"
8 #include <dt-bindings/soc/imx_rsrc.h>
9 #include <dt-bindings/soc/imx8_pd.h>
10 #include <dt-bindings/clock/imx8qxp-clock.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
13 #include <dt-bindings/gpio/gpio.h>
16 model = "Freescale i.MX8DX";
17 compatible = "fsl,imx8dx", "fsl,imx8qxp";
18 interrupt-parent = <&gic>;
36 device_type = "memory";
37 reg = <0x00000000 0x80000000 0 0x40000000>;
38 /* DRAM space - 1, size : 1 GB DRAM */
47 * reserved-memory layout
48 * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
49 * Shouldn't be used at A core and Linux side.
52 decoder_boot: decoder_boot@0x84000000 {
54 reg = <0 0x84000000 0 0x2000000>;
56 encoder_boot: encoder_boot@0x86000000 {
58 reg = <0 0x86000000 0 0x2000000>;
60 rpmsg_reserved: rpmsg@0x90000000 {
62 reg = <0 0x90000000 0 0x400000>;
64 decoder_rpc: decoder_rpc@0x90400000 {
66 reg = <0 0x90400000 0 0x1000000>;
68 encoder_rpc: encoder_rpc@0x91400000 {
70 reg = <0 0x91400000 0 0x1000000>;
72 dsp_reserved: dsp@0x92400000 {
74 reg = <0 0x92400000 0 0x2000000>;
76 decoder_str: str@0x94400000 {
78 reg = <0 0x94400000 0 0x1800000>;
80 /* global autoconfigured region for contiguous allocations */
82 compatible = "shared-dma-pool";
84 size = <0 0x28000000>;
85 alloc-ranges = <0 0x96000000 0 0x28000000>;
90 gic: interrupt-controller@51a00000 {
91 compatible = "arm,gic-v3";
92 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
93 <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
94 #interrupt-cells = <3>;
96 interrupts = <GIC_PPI 9
97 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
98 interrupt-parent = <&gic>;
102 compatible = "fsl,imx8-mu";
103 reg = <0x0 0x5d1c0000 0x0 0x10000>;
104 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
105 interrupt-parent = <&gic>;
109 compatible = "fsl,imx8qxp-clk";
114 compatible = "fsl,imx8qxp-iomuxc";
119 compatible = "simple-bus";
120 #address-cells = <1>;
124 compatible = "nxp,imx8-pd";
126 #power-domain-cells = <0>;
127 #address-cells = <1>;
130 pd_lsio_gpio0: PD_LSIO_GPIO_0 {
132 #power-domain-cells = <0>;
133 power-domains = <&pd_lsio>;
135 pd_lsio_gpio1: PD_LSIO_GPIO_1 {
137 #power-domain-cells = <0>;
138 power-domains = <&pd_lsio>;
140 pd_lsio_gpio2: PD_LSIO_GPIO_2 {
142 #power-domain-cells = <0>;
143 power-domains = <&pd_lsio>;
145 pd_lsio_gpio3: PD_LSIO_GPIO_3 {
147 #power-domain-cells = <0>;
148 power-domains = <&pd_lsio>;
150 pd_lsio_gpio4: PD_LSIO_GPIO_4 {
152 #power-domain-cells = <0>;
153 power-domains = <&pd_lsio>;
155 pd_lsio_gpio5: PD_LSIO_GPIO_5{
157 #power-domain-cells = <0>;
158 power-domains = <&pd_lsio>;
160 pd_lsio_gpio6: PD_LSIO_GPIO_6 {
162 #power-domain-cells = <0>;
163 power-domains = <&pd_lsio>;
165 pd_lsio_gpio7: PD_LSIO_GPIO_7 {
167 #power-domain-cells = <0>;
168 power-domains = <&pd_lsio>;
173 compatible = "nxp,imx8-pd";
175 #power-domain-cells = <0>;
176 #address-cells = <1>;
179 pd_conn_sdch0: PD_CONN_SDHC_0 {
181 #power-domain-cells = <0>;
182 power-domains = <&pd_conn>;
184 pd_conn_sdch1: PD_CONN_SDHC_1 {
186 #power-domain-cells = <0>;
187 power-domains = <&pd_conn>;
189 pd_conn_sdch2: PD_CONN_SDHC_2 {
191 #power-domain-cells = <0>;
192 power-domains = <&pd_conn>;
194 pd_conn_enet0: PD_CONN_ENET_0 {
196 #power-domain-cells = <0>;
197 power-domains = <&pd_conn>;
199 pd_conn_enet1: PD_CONN_ENET_1 {
201 #power-domain-cells = <0>;
202 power-domains = <&pd_conn>;
207 compatible = "nxp,imx8-pd";
209 #power-domain-cells = <0>;
210 #address-cells = <1>;
213 pd_dma_lpi2c0: PD_DMA_I2C_0 {
215 #power-domain-cells = <0>;
216 power-domains = <&pd_dma>;
218 pd_dma_lpi2c1: PD_DMA_I2C_1 {
220 #power-domain-cells = <0>;
221 power-domains = <&pd_dma>;
223 pd_dma_lpi2c2:PD_DMA_I2C_2 {
225 #power-domain-cells = <0>;
226 power-domains = <&pd_dma>;
228 pd_dma_lpi2c3: PD_DMA_I2C_3 {
230 #power-domain-cells = <0>;
231 power-domains = <&pd_dma>;
233 pd_dma_lpuart0: PD_DMA_UART0 {
235 #power-domain-cells = <0>;
236 power-domains = <&pd_dma>;
239 pd_dma_lpuart1: PD_DMA_UART1 {
241 #power-domain-cells = <0>;
242 power-domains = <&pd_dma>;
244 pd_dma_lpuart2: PD_DMA_UART2 {
246 #power-domain-cells = <0>;
247 power-domains = <&pd_dma>;
249 pd_dma_lpuart3: PD_DMA_UART3 {
251 #power-domain-cells = <0>;
252 power-domains = <&pd_dma>;
258 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
259 reg = <0x0 0x5a800000 0x0 0x4000>;
260 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
261 interrupt-parent = <&gic>;
262 clocks = <&clk IMX8QXP_I2C0_CLK>;
264 assigned-clocks = <&clk IMX8QXP_I2C0_CLK>;
265 assigned-clock-rates = <24000000>;
266 power-domains = <&pd_dma_lpi2c0>;
267 #address-cells = <1>;
273 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
274 reg = <0x0 0x5a810000 0x0 0x4000>;
275 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
276 interrupt-parent = <&gic>;
277 clocks = <&clk IMX8QXP_I2C1_CLK>,
278 <&clk IMX8QXP_I2C1_IPG_CLK>;
279 clock-names = "per", "ipg";
280 assigned-clocks = <&clk IMX8QXP_I2C1_CLK>;
281 assigned-clock-rates = <24000000>;
282 power-domains = <&pd_dma_lpi2c1>;
283 #address-cells = <1>;
289 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
290 reg = <0x0 0x5a820000 0x0 0x4000>;
291 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
292 interrupt-parent = <&gic>;
293 clocks = <&clk IMX8QXP_I2C2_CLK>;
295 assigned-clocks = <&clk IMX8QXP_I2C2_CLK>;
296 assigned-clock-rates = <24000000>;
297 power-domains = <&pd_dma_lpi2c2>;
298 #address-cells = <1>;
304 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
305 reg = <0x0 0x5a830000 0x0 0x4000>;
306 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
307 interrupt-parent = <&gic>;
308 clocks = <&clk IMX8QXP_I2C3_CLK>,
309 <&clk IMX8QXP_I2C3_IPG_CLK>;
310 clock-names = "per", "ipg";
311 assigned-clocks = <&clk IMX8QXP_I2C3_CLK>;
312 assigned-clock-rates = <24000000>;
313 power-domains = <&pd_dma_lpi2c3>;
314 #address-cells = <1>;
319 gpio0: gpio@5d080000 {
320 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
321 reg = <0x0 0x5d080000 0x0 0x10000>;
322 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
325 power-domains = <&pd_lsio_gpio0>;
326 interrupt-controller;
327 #interrupt-cells = <2>;
330 gpio1: gpio@5d090000 {
331 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
332 reg = <0x0 0x5d090000 0x0 0x10000>;
333 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
336 power-domains = <&pd_lsio_gpio1>;
337 interrupt-controller;
338 #interrupt-cells = <2>;
341 gpio2: gpio@5d0a0000 {
342 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
343 reg = <0x0 0x5d0a0000 0x0 0x10000>;
344 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
347 power-domains = <&pd_lsio_gpio2>;
348 interrupt-controller;
349 #interrupt-cells = <2>;
352 gpio3: gpio@5d0b0000 {
353 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
354 reg = <0x0 0x5d0b0000 0x0 0x10000>;
355 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
358 power-domains = <&pd_lsio_gpio3>;
359 interrupt-controller;
360 #interrupt-cells = <2>;
363 gpio4: gpio@5d0c0000 {
364 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
365 reg = <0x0 0x5d0c0000 0x0 0x10000>;
366 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
369 power-domains = <&pd_lsio_gpio4>;
370 interrupt-controller;
371 #interrupt-cells = <2>;
374 gpio5: gpio@5d0d0000 {
375 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
376 reg = <0x0 0x5d0d0000 0x0 0x10000>;
377 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
380 power-domains = <&pd_lsio_gpio5>;
381 interrupt-controller;
382 #interrupt-cells = <2>;
385 gpio6: gpio@5d0e0000 {
386 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
387 reg = <0x0 0x5d0e0000 0x0 0x10000>;
388 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
391 power-domains = <&pd_lsio_gpio6>;
392 interrupt-controller;
393 #interrupt-cells = <2>;
396 gpio7: gpio@5d0f0000 {
397 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
398 reg = <0x0 0x5d0f0000 0x0 0x10000>;
399 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
402 power-domains = <&pd_lsio_gpio7>;
403 interrupt-controller;
404 #interrupt-cells = <2>;
407 lpuart0: serial@5a060000 {
408 compatible = "fsl,imx8qm-lpuart";
409 reg = <0x0 0x5a060000 0x0 0x1000>;
410 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&clk IMX8QXP_UART0_CLK>,
412 <&clk IMX8QXP_UART0_IPG_CLK>;
413 clock-names = "per", "ipg";
414 assigned-clocks = <&clk IMX8QXP_UART0_CLK>;
415 assigned-clock-rates = <80000000>;
416 power-domains = <&pd_dma_lpuart0>;
420 lpuart1: serial@5a070000 {
421 compatible = "fsl,imx8qm-lpuart";
422 reg = <0x0 0x5a070000 0x0 0x1000>;
423 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
424 clocks = <&clk IMX8QXP_UART1_CLK>,
425 <&clk IMX8QXP_UART1_IPG_CLK>;
426 clock-names = "per", "ipg";
427 assigned-clocks = <&clk IMX8QXP_UART1_CLK>;
428 assigned-clock-rates = <80000000>;
429 power-domains = <&pd_dma_lpuart1>;
433 lpuart2: serial@5a080000 {
434 compatible = "fsl,imx8qm-lpuart";
435 reg = <0x0 0x5a080000 0x0 0x1000>;
436 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&clk IMX8QXP_UART2_CLK>,
438 <&clk IMX8QXP_UART2_IPG_CLK>;
439 clock-names = "per", "ipg";
440 assigned-clocks = <&clk IMX8QXP_UART2_CLK>;
441 assigned-clock-rates = <80000000>;
442 power-domains = <&pd_dma_lpuart2>;
446 lpuart3: serial@5a090000 {
447 compatible = "fsl,imx8qm-lpuart";
448 reg = <0x0 0x5a090000 0x0 0x1000>;
449 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
450 clocks = <&clk IMX8QXP_UART3_CLK>,
451 <&clk IMX8QXP_UART3_IPG_CLK>;
452 clock-names = "per", "ipg";
453 assigned-clocks = <&clk IMX8QXP_UART3_CLK>;
454 assigned-clock-rates = <80000000>;
455 power-domains = <&pd_dma_lpuart3>;
459 usdhc1: usdhc@5b010000 {
460 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
461 interrupt-parent = <&gic>;
462 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
463 reg = <0x0 0x5b010000 0x0 0x10000>;
464 clocks = <&clk IMX8QXP_SDHC0_IPG_CLK>,
465 <&clk IMX8QXP_SDHC0_CLK>,
466 <&clk IMX8QXP_CLK_DUMMY>;
467 clock-names = "ipg", "per", "ahb";
468 assigned-clocks = <&clk IMX8QXP_SDHC0_SEL>, <&clk IMX8QXP_SDHC0_DIV>;
469 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
470 assigned-clock-rates = <0>, <400000000>;
471 power-domains = <&pd_conn_sdch0>;
472 fsl,tuning-start-tap = <20>;
473 fsl,tuning-step= <2>;
477 usdhc2: usdhc@5b020000 {
478 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
479 interrupt-parent = <&gic>;
480 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
481 reg = <0x0 0x5b020000 0x0 0x10000>;
482 clocks = <&clk IMX8QXP_SDHC1_IPG_CLK>,
483 <&clk IMX8QXP_SDHC1_CLK>,
484 <&clk IMX8QXP_CLK_DUMMY>;
485 clock-names = "ipg", "per", "ahb";
486 assigned-clocks = <&clk IMX8QXP_SDHC1_SEL>, <&clk IMX8QXP_SDHC1_DIV>;
487 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
488 assigned-clock-rates = <0>, <200000000>;
489 power-domains = <&pd_conn_sdch1>;
490 fsl,tuning-start-tap = <20>;
491 fsl,tuning-step= <2>;
495 usdhc3: usdhc@5b030000 {
496 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
497 interrupt-parent = <&gic>;
498 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
499 reg = <0x0 0x5b030000 0x0 0x10000>;
500 clocks = <&clk IMX8QXP_SDHC2_IPG_CLK>,
501 <&clk IMX8QXP_SDHC2_CLK>,
502 <&clk IMX8QXP_CLK_DUMMY>;
503 clock-names = "ipg", "per", "ahb";
504 assigned-clocks = <&clk IMX8QXP_SDHC2_SEL>, <&clk IMX8QXP_SDHC2_DIV>;
505 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
506 assigned-clock-rates = <0>, <200000000>;
507 power-domains = <&pd_conn_sdch2>;
511 fec1: ethernet@5b040000 {
512 compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec";
513 reg = <0x0 0x5b040000 0x0 0x10000>;
514 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, <&clk IMX8QXP_ENET0_AHB_CLK>,
519 <&clk IMX8QXP_ENET0_RGMII_TX_CLK>, <&clk IMX8QXP_ENET0_PTP_CLK>;
520 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
521 assigned-clocks = <&clk IMX8QXP_ENET0_REF_DIV>, <&clk IMX8QXP_ENET0_PTP_CLK>;
522 assigned-clock-rates = <125000000>, <125000000>;
523 fsl,num-tx-queues=<3>;
524 fsl,num-rx-queues=<3>;
525 power-domains = <&pd_conn_enet0>;
529 fec2: ethernet@5b050000 {
530 compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec";
531 reg = <0x0 0x5b050000 0x0 0x10000>;
532 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&clk IMX8QXP_ENET1_IPG_CLK>, <&clk IMX8QXP_ENET1_AHB_CLK>,
537 <&clk IMX8QXP_ENET1_RGMII_TX_CLK>, <&clk IMX8QXP_ENET1_PTP_CLK>;
538 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
539 assigned-clocks = <&clk IMX8QXP_ENET1_REF_DIV>, <&clk IMX8QXP_ENET1_PTP_CLK>;
540 assigned-clock-rates = <125000000>, <125000000>;
541 fsl,num-tx-queues=<3>;
542 fsl,num-rx-queues=<3>;
543 power-domains = <&pd_conn_enet1>;
549 clocks = <&clk IMX8QXP_A35_DIV>;
552 /delete-node/ &A35_2;
553 /delete-node/ &A35_3;