1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include "fsl-imx8-ca35.dtsi"
8 #include <dt-bindings/soc/imx_rsrc.h>
9 #include <dt-bindings/soc/imx8_pd.h>
10 #include <dt-bindings/clock/imx8qxp-clock.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
13 #include <dt-bindings/gpio/gpio.h>
16 model = "Freescale i.MX8DX";
17 compatible = "fsl,imx8dx", "fsl,imx8qxp";
18 interrupt-parent = <&gic>;
36 device_type = "memory";
37 reg = <0x00000000 0x80000000 0 0x40000000>;
38 /* DRAM space - 1, size : 1 GB DRAM */
47 * reserved-memory layout
48 * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
49 * Shouldn't be used at A core and Linux side.
52 decoder_boot: decoder_boot@0x84000000 {
54 reg = <0 0x84000000 0 0x2000000>;
56 encoder_boot: encoder_boot@0x86000000 {
58 reg = <0 0x86000000 0 0x2000000>;
60 rpmsg_reserved: rpmsg@0x90000000 {
62 reg = <0 0x90000000 0 0x400000>;
64 decoder_rpc: decoder_rpc@0x90400000 {
66 reg = <0 0x90400000 0 0x1000000>;
68 encoder_rpc: encoder_rpc@0x91400000 {
70 reg = <0 0x91400000 0 0x1000000>;
72 dsp_reserved: dsp@0x92400000 {
74 reg = <0 0x92400000 0 0x2000000>;
76 decoder_str: str@0x94400000 {
78 reg = <0 0x94400000 0 0x1800000>;
80 /* global autoconfigured region for contiguous allocations */
82 compatible = "shared-dma-pool";
84 size = <0 0x28000000>;
85 alloc-ranges = <0 0x96000000 0 0x28000000>;
90 gic: interrupt-controller@51a00000 {
91 compatible = "arm,gic-v3";
92 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
93 <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
94 #interrupt-cells = <3>;
96 interrupts = <GIC_PPI 9
97 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
98 interrupt-parent = <&gic>;
102 compatible = "fsl,imx8-mu";
103 reg = <0x0 0x5d1c0000 0x0 0x10000>;
104 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
105 interrupt-parent = <&gic>;
109 compatible = "fsl,imx8qxp-clk";
114 compatible = "fsl,imx8qxp-iomuxc";
119 compatible = "simple-bus";
120 #address-cells = <1>;
124 compatible = "nxp,imx8-pd";
126 #power-domain-cells = <0>;
127 #address-cells = <1>;
130 pd_lsio_gpio0: PD_LSIO_GPIO_0 {
132 #power-domain-cells = <0>;
133 power-domains = <&pd_lsio>;
135 pd_lsio_gpio1: PD_LSIO_GPIO_1 {
137 #power-domain-cells = <0>;
138 power-domains = <&pd_lsio>;
140 pd_lsio_gpio2: PD_LSIO_GPIO_2 {
142 #power-domain-cells = <0>;
143 power-domains = <&pd_lsio>;
145 pd_lsio_gpio3: PD_LSIO_GPIO_3 {
147 #power-domain-cells = <0>;
148 power-domains = <&pd_lsio>;
150 pd_lsio_gpio4: PD_LSIO_GPIO_4 {
152 #power-domain-cells = <0>;
153 power-domains = <&pd_lsio>;
155 pd_lsio_gpio5: PD_LSIO_GPIO_5{
157 #power-domain-cells = <0>;
158 power-domains = <&pd_lsio>;
160 pd_lsio_gpio6: PD_LSIO_GPIO_6 {
162 #power-domain-cells = <0>;
163 power-domains = <&pd_lsio>;
165 pd_lsio_gpio7: PD_LSIO_GPIO_7 {
167 #power-domain-cells = <0>;
168 power-domains = <&pd_lsio>;
173 compatible = "nxp,imx8-pd";
175 #power-domain-cells = <0>;
176 #address-cells = <1>;
179 pd_conn_sdch0: PD_CONN_SDHC_0 {
181 #power-domain-cells = <0>;
182 power-domains = <&pd_conn>;
184 pd_conn_sdch1: PD_CONN_SDHC_1 {
186 #power-domain-cells = <0>;
187 power-domains = <&pd_conn>;
189 pd_conn_sdch2: PD_CONN_SDHC_2 {
191 #power-domain-cells = <0>;
192 power-domains = <&pd_conn>;
194 pd_conn_enet0: PD_CONN_ENET_0 {
196 #power-domain-cells = <0>;
197 power-domains = <&pd_conn>;
199 pd_conn_enet1: PD_CONN_ENET_1 {
201 #power-domain-cells = <0>;
202 power-domains = <&pd_conn>;
207 compatible = "nxp,imx8-pd";
209 #power-domain-cells = <0>;
210 #address-cells = <1>;
213 pd_dma_lpi2c0: PD_DMA_I2C_0 {
215 #power-domain-cells = <0>;
216 power-domains = <&pd_dma>;
218 pd_dma_lpi2c1: PD_DMA_I2C_1 {
220 #power-domain-cells = <0>;
221 power-domains = <&pd_dma>;
223 pd_dma_lpi2c2:PD_DMA_I2C_2 {
225 #power-domain-cells = <0>;
226 power-domains = <&pd_dma>;
228 pd_dma_lpi2c3: PD_DMA_I2C_3 {
230 #power-domain-cells = <0>;
231 power-domains = <&pd_dma>;
233 pd_dma_lpuart0: PD_DMA_UART0 {
235 #power-domain-cells = <0>;
236 power-domains = <&pd_dma>;
243 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
244 reg = <0x0 0x5a800000 0x0 0x4000>;
245 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
246 interrupt-parent = <&gic>;
247 clocks = <&clk IMX8QXP_I2C0_CLK>;
249 assigned-clocks = <&clk IMX8QXP_I2C0_CLK>;
250 assigned-clock-rates = <24000000>;
251 power-domains = <&pd_dma_lpi2c0>;
252 #address-cells = <1>;
258 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
259 reg = <0x0 0x5a810000 0x0 0x4000>;
260 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
261 interrupt-parent = <&gic>;
262 clocks = <&clk IMX8QXP_I2C1_CLK>,
263 <&clk IMX8QXP_I2C1_IPG_CLK>;
264 clock-names = "per", "ipg";
265 assigned-clocks = <&clk IMX8QXP_I2C1_CLK>;
266 assigned-clock-rates = <24000000>;
267 power-domains = <&pd_dma_lpi2c1>;
268 #address-cells = <1>;
274 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
275 reg = <0x0 0x5a820000 0x0 0x4000>;
276 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
277 interrupt-parent = <&gic>;
278 clocks = <&clk IMX8QXP_I2C2_CLK>;
280 assigned-clocks = <&clk IMX8QXP_I2C2_CLK>;
281 assigned-clock-rates = <24000000>;
282 power-domains = <&pd_dma_lpi2c2>;
283 #address-cells = <1>;
289 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
290 reg = <0x0 0x5a830000 0x0 0x4000>;
291 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
292 interrupt-parent = <&gic>;
293 clocks = <&clk IMX8QXP_I2C3_CLK>,
294 <&clk IMX8QXP_I2C3_IPG_CLK>;
295 clock-names = "per", "ipg";
296 assigned-clocks = <&clk IMX8QXP_I2C3_CLK>;
297 assigned-clock-rates = <24000000>;
298 power-domains = <&pd_dma_lpi2c3>;
299 #address-cells = <1>;
304 gpio0: gpio@5d080000 {
305 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
306 reg = <0x0 0x5d080000 0x0 0x10000>;
307 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
310 power-domains = <&pd_lsio_gpio0>;
311 interrupt-controller;
312 #interrupt-cells = <2>;
315 gpio1: gpio@5d090000 {
316 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
317 reg = <0x0 0x5d090000 0x0 0x10000>;
318 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
321 power-domains = <&pd_lsio_gpio1>;
322 interrupt-controller;
323 #interrupt-cells = <2>;
326 gpio2: gpio@5d0a0000 {
327 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
328 reg = <0x0 0x5d0a0000 0x0 0x10000>;
329 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
332 power-domains = <&pd_lsio_gpio2>;
333 interrupt-controller;
334 #interrupt-cells = <2>;
337 gpio3: gpio@5d0b0000 {
338 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
339 reg = <0x0 0x5d0b0000 0x0 0x10000>;
340 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
343 power-domains = <&pd_lsio_gpio3>;
344 interrupt-controller;
345 #interrupt-cells = <2>;
348 gpio4: gpio@5d0c0000 {
349 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
350 reg = <0x0 0x5d0c0000 0x0 0x10000>;
351 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
354 power-domains = <&pd_lsio_gpio4>;
355 interrupt-controller;
356 #interrupt-cells = <2>;
359 gpio5: gpio@5d0d0000 {
360 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
361 reg = <0x0 0x5d0d0000 0x0 0x10000>;
362 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
365 power-domains = <&pd_lsio_gpio5>;
366 interrupt-controller;
367 #interrupt-cells = <2>;
370 gpio6: gpio@5d0e0000 {
371 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
372 reg = <0x0 0x5d0e0000 0x0 0x10000>;
373 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
376 power-domains = <&pd_lsio_gpio6>;
377 interrupt-controller;
378 #interrupt-cells = <2>;
381 gpio7: gpio@5d0f0000 {
382 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
383 reg = <0x0 0x5d0f0000 0x0 0x10000>;
384 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
387 power-domains = <&pd_lsio_gpio7>;
388 interrupt-controller;
389 #interrupt-cells = <2>;
392 lpuart0: serial@5a060000 {
393 compatible = "fsl,imx8qm-lpuart";
394 reg = <0x0 0x5a060000 0x0 0x1000>;
395 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&clk IMX8QXP_UART0_CLK>,
397 <&clk IMX8QXP_UART0_IPG_CLK>;
398 clock-names = "per", "ipg";
399 assigned-clocks = <&clk IMX8QXP_UART0_CLK>;
400 assigned-clock-rates = <80000000>;
401 power-domains = <&pd_dma_lpuart0>;
405 usdhc1: usdhc@5b010000 {
406 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
407 interrupt-parent = <&gic>;
408 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
409 reg = <0x0 0x5b010000 0x0 0x10000>;
410 clocks = <&clk IMX8QXP_SDHC0_IPG_CLK>,
411 <&clk IMX8QXP_SDHC0_CLK>,
412 <&clk IMX8QXP_CLK_DUMMY>;
413 clock-names = "ipg", "per", "ahb";
414 assigned-clocks = <&clk IMX8QXP_SDHC0_SEL>, <&clk IMX8QXP_SDHC0_DIV>;
415 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
416 assigned-clock-rates = <0>, <400000000>;
417 power-domains = <&pd_conn_sdch0>;
418 fsl,tuning-start-tap = <20>;
419 fsl,tuning-step= <2>;
423 usdhc2: usdhc@5b020000 {
424 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
425 interrupt-parent = <&gic>;
426 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
427 reg = <0x0 0x5b020000 0x0 0x10000>;
428 clocks = <&clk IMX8QXP_SDHC1_IPG_CLK>,
429 <&clk IMX8QXP_SDHC1_CLK>,
430 <&clk IMX8QXP_CLK_DUMMY>;
431 clock-names = "ipg", "per", "ahb";
432 assigned-clocks = <&clk IMX8QXP_SDHC1_SEL>, <&clk IMX8QXP_SDHC1_DIV>;
433 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
434 assigned-clock-rates = <0>, <200000000>;
435 power-domains = <&pd_conn_sdch1>;
436 fsl,tuning-start-tap = <20>;
437 fsl,tuning-step= <2>;
441 usdhc3: usdhc@5b030000 {
442 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
443 interrupt-parent = <&gic>;
444 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
445 reg = <0x0 0x5b030000 0x0 0x10000>;
446 clocks = <&clk IMX8QXP_SDHC2_IPG_CLK>,
447 <&clk IMX8QXP_SDHC2_CLK>,
448 <&clk IMX8QXP_CLK_DUMMY>;
449 clock-names = "ipg", "per", "ahb";
450 assigned-clocks = <&clk IMX8QXP_SDHC2_SEL>, <&clk IMX8QXP_SDHC2_DIV>;
451 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
452 assigned-clock-rates = <0>, <200000000>;
453 power-domains = <&pd_conn_sdch2>;
457 fec1: ethernet@5b040000 {
458 compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec";
459 reg = <0x0 0x5b040000 0x0 0x10000>;
460 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, <&clk IMX8QXP_ENET0_AHB_CLK>,
465 <&clk IMX8QXP_ENET0_RGMII_TX_CLK>, <&clk IMX8QXP_ENET0_PTP_CLK>;
466 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
467 assigned-clocks = <&clk IMX8QXP_ENET0_REF_DIV>, <&clk IMX8QXP_ENET0_PTP_CLK>;
468 assigned-clock-rates = <125000000>, <125000000>;
469 fsl,num-tx-queues=<3>;
470 fsl,num-rx-queues=<3>;
471 power-domains = <&pd_conn_enet0>;
475 fec2: ethernet@5b050000 {
476 compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec";
477 reg = <0x0 0x5b050000 0x0 0x10000>;
478 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
479 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
481 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&clk IMX8QXP_ENET1_IPG_CLK>, <&clk IMX8QXP_ENET1_AHB_CLK>,
483 <&clk IMX8QXP_ENET1_RGMII_TX_CLK>, <&clk IMX8QXP_ENET1_PTP_CLK>;
484 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
485 assigned-clocks = <&clk IMX8QXP_ENET1_REF_DIV>, <&clk IMX8QXP_ENET1_PTP_CLK>;
486 assigned-clock-rates = <125000000>, <125000000>;
487 fsl,num-tx-queues=<3>;
488 fsl,num-rx-queues=<3>;
489 power-domains = <&pd_conn_enet1>;
495 clocks = <&clk IMX8QXP_A35_DIV>;
498 /delete-node/ &A35_2;
499 /delete-node/ &A35_3;