arch/arm/dts/fsl-imx8-ca53.dtsi

   1 /*
   2  * Copyright 2017 NXP
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 /{
  16         cpus {
  17                 #address-cells = <2>;
  18                 #size-cells = <0>;
  19
  20                 idle-states {
  21                         entry-method = "psci";
  22
  23                         CPU_SLEEP: cpu-sleep {
  24                                 compatible = "arm,idle-state";
  25                                 local-timer-stop;
  26                                 arm,psci-suspend-param = <0x0000000>;
  27                                 entry-latency-us = <700>;
  28                                 exit-latency-us = <250>;
  29                                 min-residency-us = <1000>;
  30                         };
  31
  32                         CLUSTER_SLEEP: cluster-sleep {
  33                                 compatible = "arm,idle-state";
  34                                 local-timer-stop;
  35                                 arm,psci-suspend-param = <0x1000000>;
  36                                 entry-latency-us = <1000>;
  37                                 exit-latency-us = <700>;
  38                                 min-residency-us = <2700>;
  39                                 wakeup-latency-us = <1500>;
  40                         };
  41                 };
  42
  43                 /* We have 1 clusters having 4 Cortex-A53 cores */
  44                 A53_0: cpu@0 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a53";
  47                         reg = <0x0 0x0>;
  48                         enable-method = "psci";
  49                         next-level-cache = <&A53_L2>;
  50                         cpu-idle-states = <&CPU_SLEEP>;
  51                 };
  52
  53                 A53_1: cpu@1 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a53";
  56                         reg = <0x0 0x1>;
  57                         enable-method = "psci";
  58                         next-level-cache = <&A53_L2>;
  59                         cpu-idle-states = <&CPU_SLEEP>;
  60                 };
  61
  62                 A53_2: cpu@2 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a53";
  65                         reg = <0x0 0x2>;
  66                         enable-method = "psci";
  67                         next-level-cache = <&A53_L2>;
  68                         cpu-idle-states = <&CPU_SLEEP>;
  69                 };
  70
  71                 A53_3: cpu@3 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a53";
  74                         reg = <0x0 0x3>;
  75                         enable-method = "psci";
  76                         next-level-cache = <&A53_L2>;
  77                         cpu-idle-states = <&CPU_SLEEP>;
  78                 };
  79
  80                 A53_L2: l2-cache0 {
  81                         compatible = "cache";
  82                 };
  83         };
  84
  85         psci {
  86                 compatible = "arm,psci-1.0";
  87                 method = "smc";
  88                 cpu_suspend   = <0xc4000001>;
  89                 cpu_off       = <0xc4000002>;
  90                 cpu_on        = <0xc4000003>;
  91         };
  92 };