arch/arm/dts/exynos7420.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Samsung Exynos7420 SoC device tree source
   4  *
   5  * Copyright (c) 2016 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  */
   8
   9 /dts-v1/;
  10 #include "skeleton.dtsi"
  11 #include <dt-bindings/clock/exynos7420-clk.h>
  12 / {
  13         compatible = "samsung,exynos7420";
  14
  15         fin_pll: xxti {
  16                 compatible = "fixed-clock";
  17                 clock-output-names = "fin_pll";
  18                 bootph-all;
  19                 #clock-cells = <0>;
  20         };
  21
  22         clock_topc: clock-controller@10570000 {
  23                 compatible = "samsung,exynos7-clock-topc";
  24                 reg = <0x10570000 0x10000>;
  25                 bootph-all;
  26                 #clock-cells = <1>;
  27                 clocks = <&fin_pll>;
  28                 clock-names = "fin_pll";
  29         };
  30
  31         clock_top0: clock-controller@105d0000 {
  32                 compatible = "samsung,exynos7-clock-top0";
  33                 reg = <0x105d0000 0xb000>;
  34                 bootph-all;
  35                 #clock-cells = <1>;
  36                 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
  37                          <&clock_topc DOUT_SCLK_BUS1_PLL>,
  38                          <&clock_topc DOUT_SCLK_CC_PLL>,
  39                          <&clock_topc DOUT_SCLK_MFC_PLL>;
  40                 clock-names = "fin_pll", "dout_sclk_bus0_pll",
  41                               "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
  42                               "dout_sclk_mfc_pll";
  43         };
  44
  45         clock_peric1: clock-controller@14c80000 {
  46                 compatible = "samsung,exynos7-clock-peric1";
  47                 reg = <0x14c80000 0xd00>;
  48                 bootph-all;
  49                 #clock-cells = <1>;
  50                 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
  51                          <&clock_top0 CLK_SCLK_UART1>,
  52                          <&clock_top0 CLK_SCLK_UART2>,
  53                          <&clock_top0 CLK_SCLK_UART3>;
  54                 clock-names = "fin_pll", "dout_aclk_peric1_66",
  55                               "sclk_uart1", "sclk_uart2", "sclk_uart3";
  56         };
  57
  58         pinctrl@13470000 {
  59                 compatible = "samsung,exynos7420-pinctrl";
  60                 reg = <0x13470000 0x1000>;
  61                 bootph-all;
  62
  63                 serial2_bus: serial2-bus {
  64                         samsung,pins = "gpd1-4", "gpd1-5";
  65                         samsung,pin-function = <2>;
  66                         samsung,pin-pud = <3>;
  67                         samsung,pin-drv = <0>;
  68                         bootph-all;
  69                 };
  70         };
  71
  72         serial@14C30000 {
  73                 compatible = "samsung,exynos4210-uart";
  74                 reg = <0x14C30000 0x100>;
  75                 bootph-all;
  76                 clocks = <&clock_peric1 PCLK_UART2>,
  77                          <&clock_peric1 SCLK_UART2>;
  78                 clock-names = "uart", "clk_uart_baud0";
  79                 pinctrl-names = "default";
  80                 pinctrl-0 = <&serial2_bus>;
  81         };
  82 };