2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include "dra72x.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
14 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
25 evm_3v3: fixedregulator-evm_3v3 {
26 compatible = "regulator-fixed";
27 regulator-name = "evm_3v3";
28 regulator-min-microvolt = <3300000>;
29 regulator-max-microvolt = <3300000>;
32 extcon_usb1: extcon_usb1 {
33 compatible = "linux,extcon-usb-gpio";
34 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
37 extcon_usb2: extcon_usb2 {
38 compatible = "linux,extcon-usb-gpio";
39 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
43 compatible = "hdmi-connector";
49 hdmi_connector_in: endpoint {
50 remote-endpoint = <&tpd12s015_out>;
56 compatible = "ti,tpd12s015";
58 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
59 <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
60 <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
69 tpd12s015_in: endpoint {
70 remote-endpoint = <&hdmi_out>;
77 tpd12s015_out: endpoint {
78 remote-endpoint = <&hdmi_connector_in>;
86 mmc1_pins_default: mmc1_pins_default {
87 pinctrl-single,pins = <
88 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
89 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
90 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
91 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
92 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
93 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
97 mmc2_pins_default: mmc2_pins_default {
98 pinctrl-single,pins = <
99 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
100 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
101 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
102 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
103 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
104 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
105 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
106 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
107 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
108 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
112 dcan1_pins_default: dcan1_pins_default {
113 pinctrl-single,pins = <
114 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
115 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
119 dcan1_pins_sleep: dcan1_pins_sleep {
120 pinctrl-single,pins = <
121 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
122 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
129 clock-frequency = <400000>;
131 tps65917: tps65917@58 {
132 compatible = "ti,tps65917";
135 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
136 interrupt-controller;
137 #interrupt-cells = <2>;
139 ti,system-power-controller;
142 compatible = "ti,tps65917-pmic";
144 tps65917_regulators: regulators {
147 regulator-name = "smps1";
148 regulator-min-microvolt = <850000>;
149 regulator-max-microvolt = <1250000>;
156 regulator-name = "smps2";
157 regulator-min-microvolt = <850000>;
158 regulator-max-microvolt = <1060000>;
164 /* VDD_GPU IVA DSPEVE */
165 regulator-name = "smps3";
166 regulator-min-microvolt = <850000>;
167 regulator-max-microvolt = <1250000>;
174 regulator-name = "smps4";
175 regulator-min-microvolt = <1800000>;
176 regulator-max-microvolt = <1800000>;
183 regulator-name = "smps5";
184 regulator-min-microvolt = <1350000>;
185 regulator-max-microvolt = <1350000>;
191 /* LDO1_OUT --> SDIO */
192 regulator-name = "ldo1";
193 regulator-min-microvolt = <1800000>;
194 regulator-max-microvolt = <3300000>;
197 regulator-allow-bypass;
202 regulator-name = "ldo3";
203 regulator-min-microvolt = <1800000>;
204 regulator-max-microvolt = <1800000>;
211 regulator-name = "ldo5";
212 regulator-min-microvolt = <1800000>;
213 regulator-max-microvolt = <1800000>;
219 /* VDDA_3V_USB: VDDA_USBHS33 */
220 regulator-name = "ldo4";
221 regulator-min-microvolt = <3300000>;
222 regulator-max-microvolt = <3300000>;
228 tps65917_power_button {
229 compatible = "ti,palmas-pwrbutton";
230 interrupt-parent = <&tps65917>;
231 interrupts = <1 IRQ_TYPE_NONE>;
233 ti,palmas-long-press-seconds = <6>;
237 pcf_gpio_21: gpio@21 {
238 compatible = "ti,pcf8575";
239 u-boot,i2c-offset-len = <0>;
241 lines-initial-states = <0x1408>;
245 interrupt-controller;
246 #interrupt-cells = <2>;
252 clock-frequency = <400000>;
254 pcf_hdmi: pcf8575@26 {
255 compatible = "nxp,pcf8575";
256 u-boot,i2c-offset-len = <0>;
261 * initial state is used here to keep the mdio interface
262 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
263 * VIN2_S0 driven high otherwise Ethernet stops working
264 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
266 lines-initial-states = <0x0f2b>;
269 /* vin6_sel_s0: high: VIN6, low: audio */
271 gpios = <1 GPIO_ACTIVE_HIGH>;
273 line-name = "vin6_sel_s0";
280 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
281 <&dra7_pmx_core 0x3e0>;
290 * For the existing IOdelay configuration via U-Boot we don't
291 * support NAND on dra72-evm. Keep it disabled. Enabling it
292 * requires a different configuration by U-Boot.
295 ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
297 /* To use NAND, DIP switch SW5 must be set like so:
298 * SW5.1 (NAND_SELn) = ON (LOW)
299 * SW5.9 (GPMC_WPN) = OFF (HIGH)
301 compatible = "ti,omap2-nand";
302 reg = <0 0 4>; /* device IO registers */
303 interrupt-parent = <&gpmc>;
304 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
305 <1 IRQ_TYPE_NONE>; /* termcount */
306 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ /* device IO registers */
307 ti,nand-ecc-opt = "bch8";
309 nand-bus-width = <16>;
310 gpmc,device-width = <2>;
311 gpmc,sync-clk-ps = <0>;
313 gpmc,cs-rd-off-ns = <80>;
314 gpmc,cs-wr-off-ns = <80>;
315 gpmc,adv-on-ns = <0>;
316 gpmc,adv-rd-off-ns = <60>;
317 gpmc,adv-wr-off-ns = <60>;
318 gpmc,we-on-ns = <10>;
319 gpmc,we-off-ns = <50>;
321 gpmc,oe-off-ns = <40>;
322 gpmc,access-ns = <40>;
323 gpmc,wr-access-ns = <80>;
324 gpmc,rd-cycle-ns = <80>;
325 gpmc,wr-cycle-ns = <80>;
326 gpmc,bus-turnaround-ns = <0>;
327 gpmc,cycle2cycle-delay-ns = <0>;
328 gpmc,clk-activation-ns = <0>;
329 gpmc,wait-monitoring-ns = <0>;
330 gpmc,wr-data-mux-bus-ns = <0>;
331 /* MTD partition table */
332 /* All SPL-* partitions are sized to minimal length
333 * which can be independently programmable. For
334 * NAND flash this is equal to size of erase-block */
335 #address-cells = <1>;
339 reg = <0x00000000 0x000020000>;
342 label = "NAND.SPL.backup1";
343 reg = <0x00020000 0x00020000>;
346 label = "NAND.SPL.backup2";
347 reg = <0x00040000 0x00020000>;
350 label = "NAND.SPL.backup3";
351 reg = <0x00060000 0x00020000>;
354 label = "NAND.u-boot-spl-os";
355 reg = <0x00080000 0x00040000>;
358 label = "NAND.u-boot";
359 reg = <0x000c0000 0x00100000>;
362 label = "NAND.u-boot-env";
363 reg = <0x001c0000 0x00020000>;
366 label = "NAND.u-boot-env.backup1";
367 reg = <0x001e0000 0x00020000>;
370 label = "NAND.kernel";
371 reg = <0x00200000 0x00800000>;
374 label = "NAND.file-system";
375 reg = <0x00a00000 0x0f600000>;
381 phy-supply = <&ldo4_reg>;
385 phy-supply = <&ldo4_reg>;
389 extcon = <&extcon_usb1>;
393 extcon = <&extcon_usb2>;
406 pinctrl-names = "default";
407 pinctrl-0 = <&mmc1_pins_default>;
408 vmmc_aux-supply = <&ldo1_reg>;
411 * SDCD signal is not being used here - using the fact that GPIO mode
412 * is a viable alternative
414 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
415 max-frequency = <192000000>;
419 /* SW5-3 in ON position */
421 pinctrl-names = "default";
422 pinctrl-0 = <&mmc2_pins_default>;
424 vmmc-supply = <&evm_3v3>;
427 max-frequency = <192000000>;
441 spi-max-frequency = <76800000>;
443 compatible = "s25fl256s1", "spi-flash";
444 spi-max-frequency = <64000000>;
446 spi-tx-bus-width = <1>;
447 spi-rx-bus-width = <4>;
448 #address-cells = <1>;
451 /* MTD partition table.
452 * The ROM checks the first four physical blocks
453 * for a valid file to boot and the flash here is
458 reg = <0x00000000 0x000010000>;
461 label = "QSPI.SPL.backup1";
462 reg = <0x00010000 0x00010000>;
465 label = "QSPI.SPL.backup2";
466 reg = <0x00020000 0x00010000>;
469 label = "QSPI.SPL.backup3";
470 reg = <0x00030000 0x00010000>;
473 label = "QSPI.u-boot";
474 reg = <0x00040000 0x00100000>;
477 label = "QSPI.u-boot-spl-os";
478 reg = <0x00140000 0x00080000>;
481 label = "QSPI.u-boot-env";
482 reg = <0x001c0000 0x00010000>;
485 label = "QSPI.u-boot-env.backup1";
486 reg = <0x001d0000 0x0010000>;
489 label = "QSPI.kernel";
490 reg = <0x001e0000 0x0800000>;
493 label = "QSPI.file-system";
494 reg = <0x009e0000 0x01620000>;
502 vdda_video-supply = <&ldo5_reg>;
510 remote-endpoint = <&tpd12s015_in>;