1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2012 DENX Software Engineering GmbH
4 * Heiko Schocher <hs@denx.de>
6 #include <dt-bindings/interrupt-controller/irq.h>
15 device_type = "memory";
16 reg = <0xc0000000 0x0>;
23 intc: interrupt-controller@fffee000 {
24 compatible = "ti,cp-intc";
26 #interrupt-cells = <1>;
28 reg = <0xfffee000 0x2000>;
33 compatible = "fixed-clock";
35 clock-output-names = "ref_clk";
37 sata_refclk: sata_refclk {
38 compatible = "fixed-clock";
40 clock-output-names = "sata_refclk";
43 usb_refclkin: usb_refclkin {
44 compatible = "fixed-clock";
46 clock-output-names = "usb_refclkin";
51 compatible = "ti,da850-dsp";
52 reg = <0x11800000 0x40000>,
57 reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig";
58 interrupt-parent = <&intc>;
65 compatible = "simple-bus";
69 ranges = <0x0 0x01c00000 0x400000>;
70 interrupt-parent = <&intc>;
72 psc0: clock-controller@10000 {
73 compatible = "ti,da850-psc0";
74 reg = <0x10000 0x1000>;
77 #power-domain-cells = <1>;
78 clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>,
79 <&pll0_sysclk 4>, <&pll0_sysclk 6>,
81 clock-names = "pll0_sysclk1", "pll0_sysclk2",
82 "pll0_sysclk4", "pll0_sysclk6",
85 pll0: clock-controller@11000 {
86 compatible = "ti,da850-pll0";
87 reg = <0x11000 0x1000>;
88 clocks = <&ref_clk>, <&pll1_sysclk 3>;
89 clock-names = "clksrc", "extclksrc";
100 pll0_obsclk: obsclk {
104 pmx_core: pinmux@14120 {
105 compatible = "pinctrl-single";
106 reg = <0x14120 0x50>;
107 #pinctrl-cells = <2>;
108 pinctrl-single,bit-per-mux;
109 pinctrl-single,register-width = <32>;
110 pinctrl-single,function-mask = <0xf>;
111 /* pin base, nr pins & gpio function */
112 pinctrl-single,gpio-range = <&range 0 17 0x8>,
120 #pinctrl-single,gpio-range-cells = <3>;
123 serial0_rtscts_pins: pinmux_serial0_rtscts_pins {
124 pinctrl-single,bits = <
125 /* UART0_RTS UART0_CTS */
126 0x0c 0x22000000 0xff000000
129 serial0_rxtx_pins: pinmux_serial0_rxtx_pins {
130 pinctrl-single,bits = <
131 /* UART0_TXD UART0_RXD */
132 0x0c 0x00220000 0x00ff0000
135 serial1_rtscts_pins: pinmux_serial1_rtscts_pins {
136 pinctrl-single,bits = <
137 /* UART1_CTS UART1_RTS */
138 0x00 0x00440000 0x00ff0000
141 serial1_rxtx_pins: pinmux_serial1_rxtx_pins {
142 pinctrl-single,bits = <
143 /* UART1_TXD UART1_RXD */
144 0x10 0x22000000 0xff000000
147 serial2_rtscts_pins: pinmux_serial2_rtscts_pins {
148 pinctrl-single,bits = <
149 /* UART2_CTS UART2_RTS */
150 0x00 0x44000000 0xff000000
153 serial2_rxtx_pins: pinmux_serial2_rxtx_pins {
154 pinctrl-single,bits = <
155 /* UART2_TXD UART2_RXD */
156 0x10 0x00220000 0x00ff0000
159 i2c0_pins: pinmux_i2c0_pins {
160 pinctrl-single,bits = <
161 /* I2C0_SDA,I2C0_SCL */
162 0x10 0x00002200 0x0000ff00
165 i2c1_pins: pinmux_i2c1_pins {
166 pinctrl-single,bits = <
167 /* I2C1_SDA, I2C1_SCL */
168 0x10 0x00440000 0x00ff0000
171 mmc0_pins: pinmux_mmc_pins {
172 pinctrl-single,bits = <
173 /* MMCSD0_DAT[3] MMCSD0_DAT[2]
174 * MMCSD0_DAT[1] MMCSD0_DAT[0]
175 * MMCSD0_CMD MMCSD0_CLK
177 0x28 0x00222222 0x00ffffff
180 ehrpwm0a_pins: pinmux_ehrpwm0a_pins {
181 pinctrl-single,bits = <
183 0xc 0x00000002 0x0000000f
186 ehrpwm0b_pins: pinmux_ehrpwm0b_pins {
187 pinctrl-single,bits = <
189 0xc 0x00000020 0x000000f0
192 ehrpwm1a_pins: pinmux_ehrpwm1a_pins {
193 pinctrl-single,bits = <
195 0x14 0x00000002 0x0000000f
198 ehrpwm1b_pins: pinmux_ehrpwm1b_pins {
199 pinctrl-single,bits = <
201 0x14 0x00000020 0x000000f0
204 ecap0_pins: pinmux_ecap0_pins {
205 pinctrl-single,bits = <
207 0x8 0x20000000 0xf0000000
210 ecap1_pins: pinmux_ecap1_pins {
211 pinctrl-single,bits = <
213 0x4 0x40000000 0xf0000000
216 ecap2_pins: pinmux_ecap2_pins {
217 pinctrl-single,bits = <
219 0x4 0x00000004 0x0000000f
222 spi0_pins: pinmux_spi0_pins {
223 pinctrl-single,bits = <
224 /* SIMO, SOMI, CLK */
225 0xc 0x00001101 0x0000ff0f
228 spi0_cs0_pin: pinmux_spi0_cs0 {
229 pinctrl-single,bits = <
231 0x10 0x00000010 0x000000f0
234 spi0_cs3_pin: pinmux_spi0_cs3_pin {
235 pinctrl-single,bits = <
237 0xc 0x01000000 0x0f000000
240 spi1_pins: pinmux_spi1_pins {
241 pinctrl-single,bits = <
242 /* SIMO, SOMI, CLK */
243 0x14 0x00110100 0x00ff0f00
246 spi1_cs0_pin: pinmux_spi1_cs0 {
247 pinctrl-single,bits = <
249 0x14 0x00000010 0x000000f0
252 mdio_pins: pinmux_mdio_pins {
253 pinctrl-single,bits = <
254 /* MDIO_CLK, MDIO_D */
255 0x10 0x00000088 0x000000ff
258 mii_pins: pinmux_mii_pins {
259 pinctrl-single,bits = <
261 * MII_TXEN, MII_TXCLK, MII_COL
262 * MII_TXD_3, MII_TXD_2, MII_TXD_1
265 0x8 0x88888880 0xfffffff0
267 * MII_RXER, MII_CRS, MII_RXCLK
268 * MII_RXDV, MII_RXD_3, MII_RXD_2
269 * MII_RXD_1, MII_RXD_0
271 0xc 0x88888888 0xffffffff
274 lcd_pins: pinmux_lcd_pins {
275 pinctrl-single,bits = <
277 * LCD_D[2], LCD_D[3], LCD_D[4], LCD_D[5],
280 0x40 0x22222200 0xffffff00
282 * LCD_D[10], LCD_D[11], LCD_D[12], LCD_D[13],
283 * LCD_D[14], LCD_D[15], LCD_D[0], LCD_D[1]
285 0x44 0x22222222 0xffffffff
286 /* LCD_D[8], LCD_D[9] */
287 0x48 0x00000022 0x000000ff
290 0x48 0x02000000 0x0f000000
291 /* LCD_AC_ENB_CS, LCD_VSYNC, LCD_HSYNC */
292 0x4c 0x02000022 0x0f0000ff
295 vpif_capture_pins: vpif_capture_pins {
296 pinctrl-single,bits = <
297 /* VP_DIN[2..7], VP_CLKIN1, VP_CLKIN0 */
298 0x38 0x11111111 0xffffffff
299 /* VP_DIN[10..15,0..1] */
300 0x3c 0x11111111 0xffffffff
302 0x40 0x00000011 0x000000ff
305 vpif_display_pins: vpif_display_pins {
306 pinctrl-single,bits = <
308 0x40 0x11111100 0xffffff00
309 /* VP_DOUT[10..15,0..1] */
310 0x44 0x11111111 0xffffffff
312 0x48 0x00000011 0x000000ff
314 * VP_CLKOUT3, VP_CLKIN3,
315 * VP_CLKOUT2, VP_CLKIN2
317 0x4c 0x00111100 0x00ffff00
321 prictrl: priority-controller@14110 {
322 compatible = "ti,da850-mstpri";
323 reg = <0x14110 0x0c>;
326 cfgchip: chip-controller@1417c {
327 compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
328 reg = <0x1417c 0x14>;
331 compatible = "ti,da830-usb-phy";
333 clocks = <&usb_phy_clk 0>, <&usb_phy_clk 1>;
334 clock-names = "usb0_clk48", "usb1_clk48";
337 usb_phy_clk: usb-phy-clocks {
338 compatible = "ti,da830-usb-phy-clocks";
340 clocks = <&psc1 1>, <&usb_refclkin>,
342 clock-names = "fck", "usb_refclkin", "auxclk";
344 ehrpwm_tbclk: ehrpwm_tbclk {
345 compatible = "ti,da830-tbclksync";
351 compatible = "ti,da830-div4p5ena";
353 clocks = <&pll0_pllout>;
354 clock-names = "pll0_pllout";
357 compatible = "ti,da850-async1-clksrc";
359 clocks = <&pll0_sysclk 3>, <&div4p5_clk>;
360 clock-names = "pll0_sysclk3", "div4.5";
363 compatible = "ti,da850-async3-clksrc";
365 clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>;
366 clock-names = "pll0_sysclk2", "pll1_sysclk2";
370 compatible = "ti,edma3-tpcc";
371 /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */
373 reg-names = "edma3_cc";
374 interrupts = <11 12>;
375 interrupt-names = "edma3_ccint", "edma3_ccerrint";
378 ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>;
379 power-domains = <&psc0 0>;
381 edma0_tptc0: tptc@8000 {
382 compatible = "ti,edma3-tptc";
383 reg = <0x8000 0x400>;
385 interrupt-names = "edm3_tcerrint";
386 power-domains = <&psc0 1>;
388 edma0_tptc1: tptc@8400 {
389 compatible = "ti,edma3-tptc";
390 reg = <0x8400 0x400>;
392 interrupt-names = "edm3_tcerrint";
393 power-domains = <&psc0 2>;
396 compatible = "ti,edma3-tpcc";
397 /* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */
398 reg = <0x230000 0x8000>;
399 reg-names = "edma3_cc";
400 interrupts = <93 94>;
401 interrupt-names = "edma3_ccint", "edma3_ccerrint";
404 ti,tptcs = <&edma1_tptc0 7>;
405 power-domains = <&psc1 0>;
407 edma1_tptc0: tptc@238000 {
408 compatible = "ti,edma3-tptc";
409 reg = <0x238000 0x400>;
411 interrupt-names = "edm3_tcerrint";
412 power-domains = <&psc1 21>;
414 serial0: serial@42000 {
415 compatible = "ti,da830-uart", "ns16550a";
416 reg = <0x42000 0x100>;
421 power-domains = <&psc0 9>;
424 serial1: serial@10c000 {
425 compatible = "ti,da830-uart", "ns16550a";
426 reg = <0x10c000 0x100>;
431 power-domains = <&psc1 12>;
434 serial2: serial@10d000 {
435 compatible = "ti,da830-uart", "ns16550a";
436 reg = <0x10d000 0x100>;
441 power-domains = <&psc1 13>;
445 compatible = "ti,da830-rtc";
446 reg = <0x23000 0x1000>;
449 clocks = <&pll0_auxclk>;
450 clock-names = "int-clk";
454 compatible = "ti,davinci-i2c";
455 reg = <0x22000 0x1000>;
457 #address-cells = <1>;
459 clocks = <&pll0_auxclk>;
463 compatible = "ti,davinci-i2c";
464 reg = <0x228000 0x1000>;
466 #address-cells = <1>;
469 power-domains = <&psc1 11>;
472 clocksource: timer@20000 {
473 compatible = "ti,da830-timer";
474 reg = <0x20000 0x1000>;
475 interrupts = <21>, <22>;
476 interrupt-names = "tint12", "tint34";
477 clocks = <&pll0_auxclk>;
480 compatible = "ti,davinci-wdt";
481 reg = <0x21000 0x1000>;
482 clocks = <&pll0_auxclk>;
486 compatible = "ti,da830-mmc";
487 reg = <0x40000 0x1000>;
491 dmas = <&edma0 16 0>, <&edma0 17 0>;
492 dma-names = "rx", "tx";
497 compatible = "ti,da850-vpif";
498 reg = <0x217000 0x1000>;
500 power-domains = <&psc1 9>;
503 /* VPIF capture port */
505 #address-cells = <1>;
509 /* VPIF display port */
511 #address-cells = <1>;
516 compatible = "ti,da830-mmc";
517 reg = <0x21b000 0x1000>;
521 dmas = <&edma1 28 0>, <&edma1 29 0>;
522 dma-names = "rx", "tx";
526 ehrpwm0: pwm@300000 {
527 compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm",
530 reg = <0x300000 0x2000>;
531 clocks = <&psc1 17>, <&ehrpwm_tbclk>;
532 clock-names = "fck", "tbclk";
533 power-domains = <&psc1 17>;
536 ehrpwm1: pwm@302000 {
537 compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm",
540 reg = <0x302000 0x2000>;
541 clocks = <&psc1 17>, <&ehrpwm_tbclk>;
542 clock-names = "fck", "tbclk";
543 power-domains = <&psc1 17>;
547 compatible = "ti,da850-ecap", "ti,am3352-ecap",
550 reg = <0x306000 0x80>;
553 power-domains = <&psc1 20>;
557 compatible = "ti,da850-ecap", "ti,am3352-ecap",
560 reg = <0x307000 0x80>;
563 power-domains = <&psc1 20>;
567 compatible = "ti,da850-ecap", "ti,am3352-ecap",
570 reg = <0x308000 0x80>;
573 power-domains = <&psc1 20>;
577 #address-cells = <1>;
579 compatible = "ti,da830-spi";
580 reg = <0x41000 0x1000>;
582 ti,davinci-spi-intr-line = <1>;
584 dmas = <&edma0 14 0>, <&edma0 15 0>;
585 dma-names = "rx", "tx";
587 power-domains = <&psc0 4>;
591 #address-cells = <1>;
593 compatible = "ti,da830-spi";
594 reg = <0x30e000 0x1000>;
596 ti,davinci-spi-intr-line = <1>;
598 dmas = <&edma0 18 0>, <&edma0 19 0>;
599 dma-names = "rx", "tx";
601 power-domains = <&psc1 10>;
605 compatible = "ti,da830-musb";
606 reg = <0x200000 0x1000>;
609 interrupt-names = "mc";
612 phy-names = "usb-phy";
617 #address-cells = <1>;
620 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
621 &cppi41dma 2 0 &cppi41dma 3 0
622 &cppi41dma 0 1 &cppi41dma 1 1
623 &cppi41dma 2 1 &cppi41dma 3 1>;
625 "rx1", "rx2", "rx3", "rx4",
626 "tx1", "tx2", "tx3", "tx4";
628 cppi41dma: dma-controller@201000 {
629 compatible = "ti,da830-cppi41";
630 reg = <0x201000 0x1000
633 reg-names = "controller",
634 "scheduler", "queuemgr";
638 power-domains = <&psc1 1>;
643 compatible = "ti,da850-ahci";
644 reg = <0x218000 0x2000>, <0x22c018 0x4>;
646 clocks = <&psc1 8>, <&sata_refclk>;
647 clock-names = "fck", "refclk";
650 pll1: clock-controller@21a000 {
651 compatible = "ti,da850-pll1";
652 reg = <0x21a000 0x1000>;
654 clock-names = "clksrc";
656 pll1_sysclk: sysclk {
659 pll1_obsclk: obsclk {
664 compatible = "ti,davinci_mdio";
665 #address-cells = <1>;
667 reg = <0x224000 0x1000>;
670 power-domains = <&psc1 5>;
673 eth0: ethernet@220000 {
674 compatible = "ti,davinci-dm6467-emac";
675 reg = <0x220000 0x4000>;
676 ti,davinci-ctrl-reg-offset = <0x3000>;
677 ti,davinci-ctrl-mod-reg-offset = <0x2000>;
678 ti,davinci-ctrl-ram-offset = <0>;
679 ti,davinci-ctrl-ram-size = <0x2000>;
680 local-mac-address = [ 00 00 00 00 00 00 ];
687 power-domains = <&psc1 5>;
691 compatible = "ti,da830-ohci";
692 reg = <0x225000 0x1000>;
695 phy-names = "usb-phy";
700 compatible = "ti,dm6441-gpio";
703 reg = <0x226000 0x1000>;
704 interrupts = <42 43 44 45 46 47 48 49 50>;
706 ti,davinci-gpio-unbanked = <0>;
708 clock-names = "gpio";
710 interrupt-controller;
711 #interrupt-cells = <2>;
712 gpio-ranges = <&pmx_core 0 15 1>,
792 <&pmx_core 80 103 1>,
793 <&pmx_core 81 102 1>,
794 <&pmx_core 82 101 1>,
795 <&pmx_core 83 100 1>,
808 <&pmx_core 96 158 1>,
809 <&pmx_core 97 157 1>,
810 <&pmx_core 98 156 1>,
811 <&pmx_core 99 155 1>,
812 <&pmx_core 100 154 1>,
813 <&pmx_core 101 129 1>,
814 <&pmx_core 102 113 1>,
815 <&pmx_core 103 112 1>,
816 <&pmx_core 104 111 1>,
817 <&pmx_core 105 110 1>,
818 <&pmx_core 106 109 1>,
819 <&pmx_core 107 108 1>,
820 <&pmx_core 108 107 1>,
821 <&pmx_core 109 106 1>,
822 <&pmx_core 110 105 1>,
823 <&pmx_core 111 104 1>,
824 <&pmx_core 112 145 1>,
825 <&pmx_core 113 144 1>,
826 <&pmx_core 114 143 1>,
827 <&pmx_core 115 142 1>,
828 <&pmx_core 116 141 1>,
829 <&pmx_core 117 140 1>,
830 <&pmx_core 118 139 1>,
831 <&pmx_core 119 138 1>,
832 <&pmx_core 120 137 1>,
833 <&pmx_core 121 136 1>,
834 <&pmx_core 122 135 1>,
835 <&pmx_core 123 134 1>,
836 <&pmx_core 124 133 1>,
837 <&pmx_core 125 132 1>,
838 <&pmx_core 126 131 1>,
839 <&pmx_core 127 130 1>,
840 <&pmx_core 128 159 1>,
841 <&pmx_core 129 31 1>,
842 <&pmx_core 130 30 1>,
843 <&pmx_core 131 20 1>,
844 <&pmx_core 132 28 1>,
845 <&pmx_core 133 27 1>,
846 <&pmx_core 134 26 1>,
847 <&pmx_core 135 23 1>,
848 <&pmx_core 136 153 1>,
849 <&pmx_core 137 152 1>,
850 <&pmx_core 138 151 1>,
851 <&pmx_core 139 150 1>,
852 <&pmx_core 140 149 1>,
853 <&pmx_core 141 148 1>,
854 <&pmx_core 142 147 1>,
855 <&pmx_core 143 146 1>;
857 psc1: clock-controller@227000 {
858 compatible = "ti,da850-psc1";
859 reg = <0x227000 0x1000>;
861 #power-domain-cells = <1>;
862 clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>,
864 clock-names = "pll0_sysclk2", "pll0_sysclk4", "async3";
865 assigned-clocks = <&async3_clk>;
866 assigned-clock-parents = <&pll1_sysclk 2>;
868 pinconf: pin-controller@22c00c {
869 compatible = "ti,da850-pupd";
870 reg = <0x22c00c 0x8>;
874 mcasp0: mcasp@100000 {
875 compatible = "ti,da830-mcasp-audio";
876 reg = <0x100000 0x2000>,
878 reg-names = "mpu", "dat";
880 interrupt-names = "common";
881 power-domains = <&psc1 7>;
885 dma-names = "tx", "rx";
888 lcdc: display@213000 {
889 compatible = "ti,da850-tilcdc";
890 reg = <0x213000 0x1000>;
892 max-pixelclock = <37500>;
895 power-domains = <&psc1 16>;
899 aemif: aemif@68000000 {
900 compatible = "ti,da850-aemif";
901 #address-cells = <2>;
904 reg = <0x68000000 0x00008000>;
905 ranges = <0 0 0x60000000 0x08000000
906 1 0 0x68000000 0x00008000>;
908 clock-names = "aemif";
912 memctrl: memory-controller@b0000000 {
913 compatible = "ti,da850-ddr-controller";
914 reg = <0xb0000000 0xe8>;