1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019 Marvell International Ltd.
6 #include "cn9130.dtsi" /* include SoC device tree */
10 compatible = "marvell,cn9130-crb",
12 "marvell,armada-ap806-quad",
13 "marvell,armada-ap806";
15 stdout-path = "serial0:115200n8";
27 device_type = "memory";
28 reg = <0x0 0x0 0x0 0x80000000>;
34 vqmmc-supply = <&cp0_reg_sd_vccq>;
35 vmmc-supply = <&cp0_reg_sd_vcc>;
37 cp0_reg_sd_vccq: cp0_sd_vccq@0 {
38 compatible = "regulator-gpio";
39 regulator-name = "cp0_sd_vccq";
40 regulator-min-microvolt = <1800000>;
41 regulator-max-microvolt = <3300000>;
42 gpios = <&cp0_gpio1 18 GPIO_ACTIVE_HIGH>;
46 cp0_reg_sd_vcc: cp0_sd_vcc@0 {
47 compatible = "regulator-fixed";
48 regulator-name = "cp0_sd_vcc";
49 regulator-min-microvolt = <3300000>;
50 regulator-max-microvolt = <3300000>;
51 gpio = <&cp0_gpio1 22 GPIO_ACTIVE_HIGH>;
64 * AP related configuration
71 /* 0 1 2 3 4 5 6 7 8 9 */
72 pin-func = < 1 1 1 1 1 1 1 1 1 1
73 1 3 1 0 0 0 0 0 0 3 >;
76 /* on-board eMMC - U6 */
78 pinctrl-names = "default";
79 pinctrl-0 = <&ap_emmc_pins>;
85 * CP related configuration
94 * [34] CP_PCIE0_CLKREQn
110 * Note that CRB board revisions have different MPP configurations.
111 * r1p2 has SPI flash on MPP[30:27] and r1p3.1, which is the latest
112 * board revision, has it mapped to MPP[16:13].
114 /* 0 1 2 3 4 5 6 7 8 9 */
115 pin-func = < 3 3 3 3 3 3 3 3 3 3
119 8 8 8 8 0 0 0 7 0 0xa
120 0 0xa 9 7 0 0xb 0xe 0xe 0xe 0xe
123 cp0_sdhci_cd_pins_crb: cp0-sdhci-cd-pins-crb {
124 marvell,pins = < 55 >;
125 marvell,function = <0>;
128 cp0_spi1_pins_crb: cp0-spi-pins-crb {
129 marvell,pins = < 13 14 15 16 >;
130 marvell,function = <3>;
133 cp0_smi_pins_crb: cp0-smi-pins-crb {
134 marvell,pins = < 40 41 >;
135 marvell,function = <8>;
138 cp0_xsmi_pins_crb: cp0-xsmi-pins-crb {
139 marvell,pins = < 42 43 >;
140 marvell,function = <8>;
149 pinctrl-names = "default";
150 pinctrl-0 = <&cp0_i2c0_pins>;
152 clock-frequency = <100000>;
156 pinctrl-names = "default";
157 pinctrl-0 = <&cp0_i2c1_pins>;
162 pinctrl-names = "default";
163 pinctrl-0 = <&cp0_sdhci_pins
164 &cp0_sdhci_cd_pins_crb>;
166 vqmmc-supply = <&cp0_reg_sd_vccq>;
167 vmmc-supply = <&cp0_reg_sd_vcc>;
172 pinctrl-names = "default";
173 pinctrl-0 = <&cp0_spi1_pins_crb>;
174 reg = <0x700680 0x50>, /* control */
175 <0x2000000 0x1000000>, /* CS0 */
176 <0 0xffffffff>, /* CS1 */
177 <0 0xffffffff>, /* CS2 */
178 <0 0xffffffff>; /* CS3 */
182 #address-cells = <0x1>;
184 compatible = "jedec,spi-nor", "spi-flash";
186 /* On-board MUX does not allow higher frequencies */
187 spi-max-frequency = <40000000>;
190 compatible = "fixed-partitions";
191 #address-cells = <1>;
196 reg = <0x0 0x200000>;
200 label = "Filesystem";
201 reg = <0x200000 0xe00000>;
216 pinctrl-names = "default";
217 pinctrl-0 = <&cp0_smi_pins_crb>;
219 phy0: ethernet-phy@0 {
222 switch6: ethernet-switch@6 {
228 pinctrl-names = "default";
229 pinctrl-0 = <&cp0_xsmi_pins_crb>;
231 nbaset_phy0: ethernet-phy@0 {
247 pinctrl-names = "default";
248 pinctrl-0 = <&cp0_ge1_rgmii_pins>;
250 phy-mode = "rgmii-id";
254 /* Disable it for now, as mainline does not support this IF yet */
256 phy = <&nbaset_phy0>;