arch/arm/dts/beacon-renesom-som.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2020, Compass Electronics Group, LLC
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7
   8 / {
   9         memory@48000000 {
  10                 device_type = "memory";
  11                 /* first 128MB is reserved for secure area. */
  12                 reg = <0x0 0x48000000 0x0 0x78000000>;
  13         };
  14
  15         memory@600000000 {
  16                 device_type = "memory";
  17                 reg = <0x6 0x00000000 0x0 0x80000000>;
  18         };
  19
  20         osc_32k: osc_32k {
  21                 compatible = "fixed-clock";
  22                 #clock-cells = <0>;
  23                 clock-frequency = <32768>;
  24                 clock-output-names = "osc_32k";
  25         };
  26
  27         reg_1p8v: regulator0 {
  28                 compatible = "regulator-fixed";
  29                 regulator-name = "fixed-1.8V";
  30                 regulator-min-microvolt = <1800000>;
  31                 regulator-max-microvolt = <1800000>;
  32                 regulator-boot-on;
  33                 regulator-always-on;
  34         };
  35
  36         reg_3p3v: regulator1 {
  37                 compatible = "regulator-fixed";
  38                 regulator-name = "fixed-3.3V";
  39                 regulator-min-microvolt = <3300000>;
  40                 regulator-max-microvolt = <3300000>;
  41                 regulator-boot-on;
  42                 regulator-always-on;
  43         };
  44
  45         wlan_pwrseq: wlan_pwrseq {
  46                 compatible = "mmc-pwrseq-simple";
  47                 reset-gpios = <&pca9654 1 GPIO_ACTIVE_LOW>;
  48                 clocks = <&osc_32k>;
  49                 clock-names = "ext_clock";
  50                 post-power-on-delay-ms = <80>;
  51         };
  52 };
  53
  54 &avb {
  55         pinctrl-0 = <&avb_pins>;
  56         pinctrl-names = "default";
  57         phy-handle = <&phy0>;
  58         phy-mode = "rgmii-id";
  59         status = "okay";
  60
  61         phy0: ethernet-phy@0 {
  62                 reg = <0>;
  63                 interrupt-parent = <&gpio2>;
  64                 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
  65                 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
  66         };
  67 };
  68
  69 &extal_clk {
  70         clock-frequency = <16666666>;
  71 };
  72
  73 &extalr_clk {
  74         clock-frequency = <32768>;
  75 };
  76
  77 &gpio6 {
  78         usb_hub_reset {
  79                 gpio-hog;
  80                 gpios = <10 GPIO_ACTIVE_HIGH>;
  81                 output-high;
  82                 line-name = "usb-hub-reset";
  83         };
  84 };
  85
  86 &hscif0 {
  87         pinctrl-0 = <&hscif0_pins>;
  88         pinctrl-names = "default";
  89         uart-has-rtscts;
  90         status = "okay";
  91         max-speed = <4000000>;
  92
  93         bluetooth {
  94                 compatible = "brcm,bcm43438-bt";
  95                 shutdown-gpios = <&pca9654 2 GPIO_ACTIVE_HIGH>;
  96                 host-wakeup-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
  97                 device-wakeup-gpios = <&pca9654 5 GPIO_ACTIVE_HIGH>;
  98                 clocks = <&osc_32k>;
  99                 clock-names = "extclk";
 100         };
 101 };
 102
 103 &hscif2 {
 104         status = "okay";
 105         pinctrl-0 = <&hscif2_pins>;
 106         pinctrl-names = "default";
 107 };
 108
 109 &i2c4 {
 110         status = "okay";
 111         clock-frequency = <400000>;
 112
 113         pca9654: gpio@20 {
 114                 compatible = "onnn,pca9654";
 115                 reg = <0x20>;
 116                 gpio-controller;
 117                 #gpio-cells = <2>;
 118                 gpio-line-names =
 119                         "i2c4_20_0",
 120                         "wl_reg_on",
 121                         "bt_reg_on",
 122                         "i2c4_20_3",
 123                         "i2c4_20_4",
 124                         "bt_dev_wake",
 125                         "i2c4_20_6",
 126                         "i2c4_20_7";
 127         };
 128
 129         pca9654_lte: gpio@21 {
 130                 compatible = "onnn,pca9654";
 131                 reg = <0x21>;
 132                 interrupt-parent = <&gpio5>;
 133                 interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
 134                 interrupt-controller;
 135                 #interrupt-cells = <2>;
 136                 gpio-controller;
 137                 #gpio-cells = <2>;
 138                 gpio-line-names =
 139                         "i2c4_21_0",
 140                         "zoe_pwr_on",
 141                         "zoe_extint",
 142                         "zoe_reset_n",
 143                         "sara_reset",
 144                         "i2c4_21_5",
 145                         "sara_pwr_off",
 146                         "sara_networking_status";
 147         };
 148
 149         eeprom@50 {
 150                 compatible = "microchip, at24c64", "atmel,24c64";
 151                 pagesize = <32>;
 152                 read-only;      /* Manufacturing EEPROM programmed at factory */
 153                 reg = <0x50>;
 154         };
 155
 156         rtc@51 {
 157                 compatible = "nxp,pcf85263";
 158                 reg = <0x51>;
 159         };
 160
 161         versaclock5: versaclock_som@6a {
 162                 compatible = "idt,5p49v6965";
 163                 reg = <0x6a>;
 164                 #clock-cells = <1>;
 165                 clocks = <&x304_clk>;
 166                 clock-names = "xin";
 167                 /* du_dotclkin0, du_dotclkin2, usb_extal, avb_txcrefclk */
 168                 assigned-clocks = <&versaclock5 1>,
 169                                    <&versaclock5 2>,
 170                                    <&versaclock5 3>,
 171                                    <&versaclock5 4>;
 172                 assigned-clock-rates = <33333333>, <33333333>, <50000000>, <125000000>;
 173         };
 174 };
 175
 176 &pfc {
 177         pinctrl-0 = <&scif_clk_pins>;
 178         pinctrl-names = "default";
 179
 180         avb_pins: avb {
 181                 mux {
 182                         groups = "avb_link", "avb_mdio", "avb_mii";
 183                         function = "avb";
 184                 };
 185
 186                 pins_mdio {
 187                         groups = "avb_mdio";
 188                         drive-strength = <24>;
 189                 };
 190
 191                 pins_mii_tx {
 192                         pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
 193                                "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
 194                         drive-strength = <12>;
 195                 };
 196         };
 197
 198         scif2_pins: scif2 {
 199                 groups = "scif2_data_a";
 200                 function = "scif2";
 201         };
 202
 203         hscif0_pins: hscif0 {
 204                 groups = "hscif0_data", "hscif0_ctrl";
 205                 function = "hscif0";
 206         };
 207
 208         hscif1_pins: hscif1 {
 209                 groups = "hscif1_data_a", "hscif1_ctrl_a";
 210                 function = "hscif1";
 211         };
 212
 213         hscif2_pins: hscif2 {
 214                 groups = "hscif2_data_a";
 215                 function = "hscif2";
 216         };
 217
 218         scif0_pins: scif0 {
 219                 groups = "scif0_data";
 220                 function = "scif0";
 221         };
 222
 223         scif5_pins: scif5 {
 224                 groups = "scif5_data_a";
 225                 function = "scif5";
 226         };
 227
 228         scif_clk_pins: scif_clk {
 229                 groups = "scif_clk_a";
 230                 function = "scif_clk";
 231         };
 232
 233         i2c0_pins: i2c0 {
 234                 groups = "i2c0";
 235                 function = "i2c0";
 236         };
 237
 238         sdhi2_pins: sd2 {
 239                 groups = "sdhi2_data4", "sdhi2_ctrl";
 240                 function = "sdhi2";
 241                 power-source = <1800>;
 242         };
 243
 244         sdhi3_pins: sd3 {
 245                 groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
 246                 function = "sdhi3";
 247                 power-source = <1800>;
 248         };
 249 };
 250
 251 &scif_clk {
 252         clock-frequency = <14745600>;
 253 };
 254
 255 &scif2 {
 256         pinctrl-0 = <&scif2_pins>;
 257         pinctrl-names = "default";
 258         status = "okay";
 259 };
 260
 261 &sdhi2 {
 262         pinctrl-names = "default";
 263         pinctrl-0 = <&sdhi2_pins>;
 264         bus-width = <4>;
 265         vmmc-supply = <&reg_3p3v>;
 266         vqmmc-supply = <&reg_1p8v>;
 267         non-removable;
 268         cap-power-off-card;
 269         pm-ignore-notify;
 270         keep-power-in-suspend;
 271         mmc-pwrseq = <&wlan_pwrseq>;
 272         status = "okay";
 273         #address-cells = <1>;
 274         #size-cells = <0>;
 275
 276         brcmf: bcrmf@1 {
 277                 reg = <1>;
 278                 compatible = "brcm,bcm4329-fmac";
 279                 interrupt-parent = <&gpio1>;
 280                 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
 281                 interrupt-names = "host-wake";
 282         };
 283 };
 284
 285 &sdhi3 {
 286         pinctrl-0 = <&sdhi3_pins>;
 287         pinctrl-1 = <&sdhi3_pins>;
 288         pinctrl-names = "default", "state_uhs";
 289         vmmc-supply = <&reg_3p3v>;
 290         vqmmc-supply = <&reg_1p8v>;
 291         bus-width = <8>;
 292         mmc-hs200-1_8v;
 293         non-removable;
 294         fixed-emmc-driver-type = <1>;
 295         status = "okay";
 296 };
 297
 298 &usb_extal_clk {
 299         clock-frequency = <50000000>;
 300 };
 301
 302 &usb3s0_clk {
 303         clock-frequency = <100000000>;
 304 };
 305
 306 &vspb {
 307         status = "okay";
 308 };
 309
 310 &vspi0 {
 311         status = "okay";
 312 };