arch/arm/dts/bcm68360.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2020 Philippe Reynes <philippe.reynes@softathome.com>
   4  */
   5
   6 #include "skeleton64.dtsi"
   7
   8 / {
   9         compatible = "brcm,bcm68360";
  10         #address-cells = <2>;
  11         #size-cells = <2>;
  12
  13         aliases {
  14                 spi0 = &hsspi;
  15         };
  16
  17         cpus {
  18                 #address-cells = <2>;
  19                 #size-cells = <0>;
  20                 u-boot,dm-pre-reloc;
  21
  22                 cpu0: cpu@0 {
  23                         compatible = "arm,cortex-a53", "arm,armv8";
  24                         device_type = "cpu";
  25                         reg = <0x0 0x0>;
  26                         next-level-cache = <&l2>;
  27                         u-boot,dm-pre-reloc;
  28                 };
  29
  30                 cpu1: cpu@1 {
  31                         compatible = "arm,cortex-a53", "arm,armv8";
  32                         device_type = "cpu";
  33                         reg = <0x0 0x1>;
  34                         next-level-cache = <&l2>;
  35                         u-boot,dm-pre-reloc;
  36                 };
  37
  38                 l2: l2-cache0 {
  39                         compatible = "cache";
  40                         u-boot,dm-pre-reloc;
  41                 };
  42         };
  43
  44         clocks {
  45                 compatible = "simple-bus";
  46                 #address-cells = <2>;
  47                 #size-cells = <2>;
  48                 ranges;
  49                 u-boot,dm-pre-reloc;
  50
  51                 periph_osc: periph-osc {
  52                         compatible = "fixed-clock";
  53                         #clock-cells = <0>;
  54                         clock-frequency = <200000000>;
  55                         u-boot,dm-pre-reloc;
  56                 };
  57
  58                 hsspi_pll: hsspi-pll {
  59                         compatible = "fixed-factor-clock";
  60                         #clock-cells = <0>;
  61                         clocks = <&periph_osc>;
  62                         clock-mult = <2>;
  63                         clock-div = <1>;
  64                 };
  65
  66                 refclk50mhz: refclk50mhz {
  67                         compatible = "fixed-clock";
  68                         #clock-cells = <0>;
  69                         clock-frequency = <50000000>;
  70                 };
  71         };
  72
  73         ubus {
  74                 compatible = "simple-bus";
  75                 #address-cells = <2>;
  76                 #size-cells = <2>;
  77                 u-boot,dm-pre-reloc;
  78
  79                 wdt1: watchdog@ff800480 {
  80                         compatible = "brcm,bcm6345-wdt";
  81                         reg = <0x0 0xff800480 0x0 0x14>;
  82                         clocks = <&refclk50mhz>;
  83                 };
  84
  85                 wdt2: watchdog@ff8004c0 {
  86                         compatible = "brcm,bcm6345-wdt";
  87                         reg = <0x0 0xff8004c0 0x0 0x14>;
  88                         clocks = <&refclk50mhz>;
  89                 };
  90
  91                 wdt-reboot {
  92                         compatible = "wdt-reboot";
  93                         wdt = <&wdt1>;
  94                 };
  95
  96                 uart0: serial@ff800640 {
  97                         compatible = "brcm,bcm6345-uart";
  98                         reg = <0x0 0xff800640 0x0 0x18>;
  99                         clocks = <&periph_osc>;
 100
 101                         status = "disabled";
 102                 };
 103
 104                 leds: led-controller@ff800800 {
 105                         compatible = "brcm,bcm6858-leds";
 106                         reg = <0x0 0xff800800 0x0 0xe4>;
 107
 108                         status = "disabled";
 109                 };
 110
 111                 gpio0: gpio-controller@0xff800500 {
 112                         compatible = "brcm,bcm6345-gpio";
 113                         reg = <0x0 0xff800500 0x0 0x4>,
 114                               <0x0 0xff800520 0x0 0x4>;
 115                         gpio-controller;
 116                         #gpio-cells = <2>;
 117
 118                         status = "disabled";
 119                 };
 120
 121                 gpio1: gpio-controller@0xff800504 {
 122                         compatible = "brcm,bcm6345-gpio";
 123                         reg = <0x0 0xff800504 0x0 0x4>,
 124                               <0x0 0xff800524 0x0 0x4>;
 125                         gpio-controller;
 126                         #gpio-cells = <2>;
 127
 128                         status = "disabled";
 129                 };
 130
 131                 gpio2: gpio-controller@0xff800508 {
 132                         compatible = "brcm,bcm6345-gpio";
 133                         reg = <0x0 0xff800508 0x0 0x4>,
 134                               <0x0 0xff800528 0x0 0x4>;
 135                         gpio-controller;
 136                         #gpio-cells = <2>;
 137
 138                         status = "disabled";
 139                 };
 140
 141                 gpio3: gpio-controller@0xff80050c {
 142                         compatible = "brcm,bcm6345-gpio";
 143                         reg = <0x0 0xff80050c 0x0 0x4>,
 144                               <0x0 0xff80052c 0x0 0x4>;
 145                         gpio-controller;
 146                         #gpio-cells = <2>;
 147
 148                         status = "disabled";
 149                 };
 150
 151                 gpio4: gpio-controller@0xff800510 {
 152                         compatible = "brcm,bcm6345-gpio";
 153                         reg = <0x0 0xff800510 0x0 0x4>,
 154                               <0x0 0xff800530 0x0 0x4>;
 155                         gpio-controller;
 156                         #gpio-cells = <2>;
 157
 158                         status = "disabled";
 159                 };
 160
 161                 gpio5: gpio-controller@0xff800514 {
 162                         compatible = "brcm,bcm6345-gpio";
 163                         reg = <0x0 0xff800514 0x0 0x4>,
 164                               <0x0 0xff800534 0x0 0x4>;
 165                         gpio-controller;
 166                         #gpio-cells = <2>;
 167
 168                         status = "disabled";
 169                 };
 170
 171                 gpio6: gpio-controller@0xff800518 {
 172                         compatible = "brcm,bcm6345-gpio";
 173                         reg = <0x0 0xff800518 0x0 0x4>,
 174                               <0x0 0xff800538 0x0 0x4>;
 175                         gpio-controller;
 176                         #gpio-cells = <2>;
 177
 178                         status = "disabled";
 179                 };
 180
 181                 gpio7: gpio-controller@0xff80051c {
 182                         compatible = "brcm,bcm6345-gpio";
 183                         reg = <0x0 0xff80051c 0x0 0x4>,
 184                               <0x0 0xff80053c 0x0 0x4>;
 185                         gpio-controller;
 186                         #gpio-cells = <2>;
 187
 188                         status = "disabled";
 189                 };
 190
 191                 hsspi: spi-controller@ff801000 {
 192                         compatible = "brcm,bcm6328-hsspi";
 193                         #address-cells = <1>;
 194                         #size-cells = <0>;
 195                         reg = <0x0 0xff801000 0x0 0x600>;
 196                         clocks = <&hsspi_pll>, <&hsspi_pll>;
 197                         clock-names = "hsspi", "pll";
 198                         spi-max-frequency = <100000000>;
 199                         num-cs = <8>;
 200
 201                         status = "disabled";
 202                 };
 203
 204                 nand: nand-controller@ff801800 {
 205                         compatible = "brcm,nand-bcm68360",
 206                                      "brcm,brcmnand-v5.0",
 207                                      "brcm,brcmnand";
 208                         reg-names = "nand", "nand-int-base", "nand-cache";
 209                         reg = <0x0 0xff801800 0x0 0x180>,
 210                               <0x0 0xff802000 0x0 0x10>,
 211                               <0x0 0xff801c00 0x0 0x200>;
 212                         parameter-page-big-endian = <0>;
 213
 214                         status = "disabled";
 215                 };
 216         };
 217 };