1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
6 #include "skeleton64.dtsi"
9 compatible = "brcm,bcm63158";
23 compatible = "arm,cortex-a53", "arm,armv8";
26 next-level-cache = <&l2>;
31 compatible = "arm,cortex-a53", "arm,armv8";
34 next-level-cache = <&l2>;
39 compatible = "arm,cortex-a53", "arm,armv8";
42 next-level-cache = <&l2>;
47 compatible = "arm,cortex-a53", "arm,armv8";
50 next-level-cache = <&l2>;
61 compatible = "simple-bus";
67 periph_osc: periph-osc {
68 compatible = "fixed-clock";
70 clock-frequency = <0xbebc200>;
74 hsspi_pll: hsspi-pll {
75 compatible = "fixed-factor-clock";
77 clocks = <&periph_osc>;
82 refclk50mhz: refclk50mhz {
83 compatible = "fixed-clock";
85 clock-frequency = <50000000>;
90 compatible = "simple-bus";
95 uart0: serial@ff812000 {
96 compatible = "arm,pl011", "arm,primecell";
97 reg = <0x0 0xff812000 0x0 0x1000>;
103 leds: led-controller@ff800800 {
104 compatible = "brcm,bcm6858-leds";
105 reg = <0x0 0xff800800 0x0 0xe4>;
110 wdt1: watchdog@ff800480 {
111 compatible = "brcm,bcm6345-wdt";
112 reg = <0x0 0xff800480 0x0 0x14>;
113 clocks = <&refclk50mhz>;
116 wdt2: watchdog@ff8004c0 {
117 compatible = "brcm,bcm6345-wdt";
118 reg = <0x0 0xff8004c0 0x0 0x14>;
119 clocks = <&refclk50mhz>;
123 compatible = "wdt-reboot";
127 gpio0: gpio-controller@0xff800500 {
128 compatible = "brcm,bcm6345-gpio";
129 reg = <0x0 0xff800500 0x0 0x4>,
130 <0x0 0xff800520 0x0 0x4>;
137 gpio1: gpio-controller@0xff800504 {
138 compatible = "brcm,bcm6345-gpio";
139 reg = <0x0 0xff800504 0x0 0x4>,
140 <0x0 0xff800524 0x0 0x4>;
147 gpio2: gpio-controller@0xff800508 {
148 compatible = "brcm,bcm6345-gpio";
149 reg = <0x0 0xff800508 0x0 0x4>,
150 <0x0 0xff800528 0x0 0x4>;
157 gpio3: gpio-controller@0xff80050c {
158 compatible = "brcm,bcm6345-gpio";
159 reg = <0x0 0xff80050c 0x0 0x4>,
160 <0x0 0xff80052c 0x0 0x4>;
167 gpio4: gpio-controller@0xff800510 {
168 compatible = "brcm,bcm6345-gpio";
169 reg = <0x0 0xff800510 0x0 0x4>,
170 <0x0 0xff800530 0x0 0x4>;
177 gpio5: gpio-controller@0xff800514 {
178 compatible = "brcm,bcm6345-gpio";
179 reg = <0x0 0xff800514 0x0 0x4>,
180 <0x0 0xff800534 0x0 0x4>;
187 gpio6: gpio-controller@0xff800518 {
188 compatible = "brcm,bcm6345-gpio";
189 reg = <0x0 0xff800518 0x0 0x4>,
190 <0x0 0xff800538 0x0 0x4>;
197 gpio7: gpio-controller@0xff80051c {
198 compatible = "brcm,bcm6345-gpio";
199 reg = <0x0 0xff80051c 0x0 0x4>,
200 <0x0 0xff80053c 0x0 0x4>;
207 hsspi: spi-controller@ff801000 {
208 compatible = "brcm,bcm6328-hsspi";
209 #address-cells = <1>;
211 reg = <0x0 0xff801000 0x0 0x600>;
212 clocks = <&hsspi_pll>, <&hsspi_pll>;
213 clock-names = "hsspi", "pll";
214 spi-max-frequency = <100000000>;
220 nand: nand-controller@ff801800 {
221 compatible = "brcm,nand-bcm63158",
222 "brcm,brcmnand-v5.0",
224 reg-names = "nand", "nand-int-base", "nand-cache";
225 reg = <0x0 0xff801800 0x0 0x180>,
226 <0x0 0xff802000 0x0 0x10>,
227 <0x0 0xff801c00 0x0 0x200>;
228 parameter-page-big-endian = <0>;