arch/arm/dts/ast2500-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/aspeed-clock.h>
   3 #include <dt-bindings/reset/ast2500-reset.h>
   4
   5 #include "ast2500.dtsi"
   6
   7 / {
   8         scu: clock-controller@1e6e2000 {
   9                 compatible = "aspeed,ast2500-scu";
  10                 reg = <0x1e6e2000 0x1000>;
  11                 u-boot,dm-pre-reloc;
  12                 #clock-cells = <1>;
  13                 #reset-cells = <1>;
  14         };
  15
  16         rst: reset-controller {
  17                 u-boot,dm-pre-reloc;
  18                 compatible = "aspeed,ast2500-reset";
  19                 aspeed,wdt = <&wdt1>;
  20                 #reset-cells = <1>;
  21         };
  22
  23         sdrammc: sdrammc@1e6e0000 {
  24                 u-boot,dm-pre-reloc;
  25                 compatible = "aspeed,ast2500-sdrammc";
  26                 reg = <0x1e6e0000 0x174
  27                         0x1e6e0200 0x1d4 >;
  28                 #reset-cells = <1>;
  29                 clocks = <&scu ASPEED_CLK_MPLL>;
  30                 resets = <&rst AST_RESET_SDRAM>;
  31         };
  32
  33         ahb {
  34                 u-boot,dm-pre-reloc;
  35
  36                 apb {
  37                         u-boot,dm-pre-reloc;
  38
  39                         sdhci0: sdhci@1e740100 {
  40                                 compatible = "aspeed,ast2500-sdhci";
  41                                 reg = <0x1e740100>;
  42                                 #reset-cells = <1>;
  43                                 clocks = <&scu ASPEED_CLK_SDIO>;
  44                                 resets = <&rst AST_RESET_SDIO>;
  45                         };
  46
  47                         sdhci1: sdhci@1e740200 {
  48                                 compatible = "aspeed,ast2500-sdhci";
  49                                 reg = <0x1e740200>;
  50                                 #reset-cells = <1>;
  51                                 clocks = <&scu ASPEED_CLK_SDIO>;
  52                                 resets = <&rst AST_RESET_SDIO>;
  53                         };
  54                 };
  55
  56         };
  57 };
  58
  59 &uart1 {
  60         clocks = <&scu ASPEED_CLK_GATE_UART1CLK>;
  61 };
  62
  63 &uart2 {
  64         clocks = <&scu ASPEED_CLK_GATE_UART2CLK>;
  65 };
  66
  67 &uart3 {
  68         clocks = <&scu ASPEED_CLK_GATE_UART3CLK>;
  69 };
  70
  71 &uart4 {
  72         clocks = <&scu ASPEED_CLK_GATE_UART4CLK>;
  73 };
  74
  75 &uart5 {
  76         clocks = <&scu ASPEED_CLK_GATE_UART5CLK>;
  77 };
  78
  79 &timer {
  80         u-boot,dm-pre-reloc;
  81 };
  82
  83 &mac0 {
  84         clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
  85 };
  86
  87 &mac1 {
  88         clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
  89 };